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參數(shù)資料
| 型號(hào)： | ADV7127KRUZ140 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VID 140MHZ 3.3/5V 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 設(shè)置時(shí)間： | 15ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 240M |
| 產(chǎn)品目錄頁(yè)面： | 786 (CN2011-ZH PDF) |
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ADV7127
–9–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9,
SYNC and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
D0–D9
Data Inputs (TTL Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.
Unused data inputs should be connected to either the regular PCB power or ground plane.
IOUT
Current Output. This high impedance current source is capable of directly driving a doubly terminated 75
coaxial cable.
RSET
Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between RSET and the full-scale output current on IOUT is given by:
IOUT (mA) = 7968
× V
REF(V)/RSET(
)
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1
F ceramic capacitor
must be connected between COMP and VAA.
VREF
Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an exter-
nal resistor divider network is not recommended. A 0.1
F decoupling ceramic capacitor should be connected
between VREF and VAA.
VAA
Analog Power Supply (5 V
± 5%). All V
AA pins on the ADV7127 must be connected.
GND
Ground. All GND pins must be connected.
IOUT
Differential Current Output. Capable of directly driving a doubly terminated 75
load. If not required, this out-
put should be tied to ground.
PSAVE
Power Save Control Pin. The part is put into standby mode when
PSAVE is low. The internal voltage reference
circuit is still active on the TSSOP in this case.
PDOWN
Power-Down Control Pin (24-Lead TSSOP Only). The ADV7127 completely powers down, including the voltage
reference circuit, when
PDOWN is low.
TERMINOLOGY
Color Video (RGB)
This usually refers to the technique of combining the three
primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that may be
visually observed.
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