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參數(shù)資料
| 型號： | ADV7123JSTZ330 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC VIDEO 3CH 330MHZ 48-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 6 電流，單極 |
| 采樣率（每秒）： | 330M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
ADV7123
Rev. D | Page 4 of 24
3.3 V SPECIFICATIONS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 2.
Parameter2
Min
Typ
Max
Unit
Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC)
10
Bits
RSET = 680 Ω
Integral Nonlinearity (BSL)
1
+0.5
+1
LSB
RSET = 680 Ω
Differential Nonlinearity
1
+0.25
+1
LSB
RSET = 680 Ω
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.8
V
Input Current, IIN
1
+1
μA
VIN = 0.0 V or VDD
PSAVE Pull-Up Current
20
μA
Input Capacitance, CIN
10
pF
ANALOG OUTPUTS
Output Current
2.0
26.5
mA
Green DAC, SYNC = high
2.0
18.5
mA
RGB DAC, SYNC = low
DAC-to-DAC Matching
1.0
%
Output Compliance Range, VOC
0
1.4
V
Output Impedance, ROUT
70
kΩ
Output Capacitance, COUT
10
pF
Offset Error
0
% FSR
Tested with DAC output = 0 V
Gain Error3
0
% FSR
FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, VREF
1.12
1.235
1.35
V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, VREF
1.235
V
POWER DISSIPATION
Digital Supply Current4
2.2
5.0
mA
fCLK = 50 MHz
6.5
12.0
mA
fCLK = 140 MHz
11
15
mA
fCLK = 240 MHz
16
mA
fCLK = 330 MHz
Analog Supply Current
67
72
mA
RSET = 560 Ω
8
mA
RSET = 4933 Ω
Standby Supply Current
2.1
5.0
mA
PSAVE = low, digital, and control inputs at VDD
Power Supply Rejection Ratio
0.1
0.5
%/%
1 Temperature range TMIN to TMAX: 40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2 These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
3 Gain error = {(Measured (FSC)/Ideal (FSC) 1) × 100}, where Ideal = VREF/RSET × K × (0x3FFH) and K = 7.9896.
4 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
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| ADV7123KSTZ140 | 功能描述:IC DAC VIDEO TRPL HI SPD 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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