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參數(shù)資料
| 型號： | ADV473KP110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ADV473KP110 |
ADV473
–5–
REV. A
PIN FUNCT ION DE SCRIPT ION
BLANK
Composite Blank Control Input (T T L Compatible). A logic zero drives the analog outputs to the blanking level.
It is latched on the rising edge of CLOCK . When
BLANK
is a logical zero, the pixel and overlay inputs are
ignored.
Composite SYNC Control Input (T T L Compatible). A logical zero on this input switches off a 40 IRE current
source on the analog outputs.
SYNC
does not override any other control or data input; therefore, it should be
asserted only during the blanking interval. It is latched on the rising edge of CLOCK . If sync information is not
required on the analog outputs,
SYNC
should be connected to ground.
Clock Input (T T L Compatible). T he rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, S0, S1,
OL0–OL3,
SYNC
, and
BLANK
inputs. It is typically the pixel clock rate of the video system. It is
recommended that CLOCK be driven by a dedicated T T L buffer.
Red, Green and Blue Select Inputs (T T L Compatible). T hese inputs specify, on a pixel basis, the color value to
be written to the DACs. T hey are latched on the rising edge of CLOCK . R0, G0 and B0 are the LSBs. Unused
inputs should be connected to GND.
Color Mode Select Inputs (T T L Compatible). T hese inputs specify the mode of operation as shown in T able III.
T hey are latched on the rising edge of CLOCK .
Overlay Select Inputs (T T L Compatible). T hese inputs specify which palette is to be used to provide color
information. When accessing the overlay palette, the R0–R7, G0–G7, B0–B7, S0 and S1 inputs are ignored. T hey
are latched on the rising edge of CLOCK . OL0 is the LSB. Unused inputs should be connected to GND.
Red, Green, and Blue Current Outputs. T hese high impedance current sources are capable of directly driving a
doubly terminated 75
coaxial cable.
Full-Scale Adjust Resistor. A resistor (R
SET
) connected between this pin and GND controls the magnitude of the
full-scale video signal. T he relationship between R
SET
and the full-scale output current on each output is:
R
SET
(
) = 3,195
×
V
REF
(V)/I
OUT
(mA) SET UP = 7.5 IRE)
R
SET
(
) = 3,025
×
V
REF
(V)/I
OUT
(mA) SET UP = 0 IRE)
Compensation Pin. T hese pins should be connected together at the chip and connected through 0.1
μ
F ceramic
capacitor to V
AA
.
Voltage Reference Input. T his input requires a 1.2 V reference voltage. T his is achieved through the on-board
voltage reference generator by connecting V
REFOUT
to V
REFIN
. If an external reference is used, it must supply
this input with a 1.2 V (typical) reference.
Voltage Reference Output. T his output delivers a 1.2 V reference voltage from the device’s on-board voltage
reference generator. It is normally connected directly to the V
REFIN
pin. If it is preferred to use an external
voltage reference, this pin may be left floating. Up to four ADV473s can be driven from V
REFOUT
.
Analog power. All V
AA
pins must be connected.
Analog Ground. All GND pins must be connected.
Write Control Input (T T L Compatible). D0–D7 data is latched on the rising edge of
WR
, and RS0–RS2 are
latched on the falling edge of
WR
during MPU write operations.
RD
and
WR
should not be asserted
simultaneously.
Read Control Input (T T L Compatible). T o read data from the device,
RD
must be a logical zero. RS0–RS2 are
latched on the falling edge of
RD
during MPU read operations.
RD
and
WR
should not be asserted
simultaneously.
Register Select Inputs (T T L Compatible). RS0–RS2 specify the type of read or write operation being performed.
Data Bus (T T L Compatible). Data is transferred into and out of the device over this eight-bit bidirectional data
bus. D0 is the least significant bit.
Control Outputs (T T L Compatible). T hese outputs are used to control application specific features. T he output
values are determined by the contents of the command register (CR).
SYNC
CLOCK
R0–R7
B0–B7
G0–G7
S0, S1
OL0–OL3
IOR, IOG, IOB
R
SET
COMP
V
REFIN
V
REFOUT
V
AA
GND
WR
RD
RS0, RS1, RS2
D0–D7
CR0–CR7
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| ADV473KP135 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV473KP135 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC |
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| ADV473KP50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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| ADV473KP80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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