參數(shù)資料
型號: ADV212BBCZ-115
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: JPEG 2000 Video Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA121
封裝: 12 X 12 MM, LEAD FREE, MO-192ABD-1, CSPBGA-121
文件頁數(shù): 22/44頁
文件大?。?/td> 374K
代理商: ADV212BBCZ-115
ADV212
Rev. 0 | Page 22 of 44
121-Ball Package
144-Ball Package
Pins
Used
1
Pin No.
63
Location
F8
Pin No.
72
Location
F12
Mnemonic
DREQ0
Type
O
Description
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 0.
FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 0 (asynchronous mode).
Valid Indication for JDATA Input/Output Stream.
Polarity of this pin is programmable in the
EDMOD0 register. VALID is always an output.
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ0) has been
acknowledged and that the data transfer can
proceed. This pin must be held high at all
times if the DMA interface is not used, even if
the DMA channels are disabled.
External Hold Indication for JDATA Input/Output
Stream. Polarity is programmable in the
EDMOD0 register. This pin is always an input.
FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 0
(asynchronous mode).
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 1.
FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed.
This pin must be held high at all times unless a
DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA
interface is not used, even if the DMA channels
are disabled.
FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 1
(asynchronous mode).
Host Expansion Bus.
FSRQ0
O
VALID
O
CFG1
I
64
F9
71
F11
DACK0
1
I
HOLD
I
FCS0
I
65
F10
70
F10
DREQ1
1
O
FSRQ1
O
CFG2
I
75
G9
69
F9
DACK1
1
I
FCS1
I
90 to 92, 78
J2 to J4, H1
111,97 to 99
K3, J1 to J3
HDATA
[31:28]
JDATA [7:4]
HDATA
[27:24]
JDATA [3:0]
4
I/O
79 to 81, 70
H2 to H4, G4
100, 85 to 87
J4, H1 to H3
4
I/O
I/O
JDATA Bus (JDATA Mode).
Host Expansion Bus.
I/O
JDATA Bus (JDATA Mode).
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