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參數(shù)資料
| 型號(hào)： | ADUM1310BRWZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | Triple-Channel Digital Isolator with Programmable Default Output |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO16 |
| 封裝： | ROHS COMPLIANT, MS-013AA, SOIC-16 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 229K |
| 代理商： | ADUM1310BRWZ-RL |
ADuM1310
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ V
DD1
≤ 3.6 V, 2.7 V ≤ V
DD2
≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.0 V; all voltages are relative to their respective ground.
Table 2.
Parameter
Symbol
Min
DC SPECIFICATIONS
ADuM1310, Total Supply Current, Three Channels
1
V
DD1
Supply Current, Quiescent
I
DD1 (Q)
V
DD2
Supply Current, Quiescent
I
DD2 (Q)
V
DD1
Supply Current, 10 Mbps Data Rate
I
DD1 (10)
V
DD2
Supply Current, 10 Mbps Data Rate
I
DD2 (10)
Input Currents
I
IA
, I
IB
, I
IC
, I
ID
,
I
CTRL
, I
DISABLE
Logic High Input Threshold
V
IH
Logic Low Input Threshold
V
IL
0.4
Logic High Output Voltages
V
OAH
, V
OBH
,
V
OCH
, V
ODH
Logic Low Output Voltages
V
OAL
, V
OBL
,
V
OCL
, V
ODL
SWITCHING SPECIFICATIONS
Minimum Pulse Width
2
PW
Maximum Data Rate
3
10
Propagation Delay
4
t
PHL
, t
PLH
20
Pulse Width Distortion, |t
PLH
– t
PHL
|
4
PWD
Change vs. Temperature
Propagation Delay Skew (Equal Temperature)
5
t
PSK
Channel-to-Channel Matching
6
t
PSKCD
Output Rise/Fall Time (10% to 90%)
t
R
/t
F
Common-Mode Transient Immunity at Logic High
Output
7
Common-Mode Transient Immunity at Logic Low
Output
7
Refresh Rate
f
r
Input Enable Time
8
t
ENABLE
Input Disable Time
8
t
DISABLE
Input Dynamic Supply Current per Channel
9
I
DDI (D)
Output Dynamic Supply Current per Channel
9
I
DDO (D)
1
Supply current values are for all channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply
current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through
Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total
I
DD1
and I
DD2
supply currents as a function of the data rate.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when V
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
DISABLE
is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (see Table 9).
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 through Figure 6 for information
on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating the per-channel supply current for a given data rate.
Rev. E | Page 4 of 16
Typ
1.2
0.8
3.4
1.1
+0.01 +10
Max Unit
1.6
1.0
4.9
1.3
Test Conditions
V
IA
= V
IB
= V
IC
= V
ID
= 0
V
IA
= V
IB
= V
IC
= V
ID
= 0
5 MHz logic signal frequency
5 MHz logic signal frequency
0 ≤ V
IA
, V
IB
, V
IC
, V
ID
, V
DISABLE
≤ V
DD1
,
0 ≤ V
CTRL
≤ V
DD2
I
Ox
= –4 mA, V
Ix
= V
IxH
mA
mA
mA
mA
μA
–10
2.8
1.6
V
V
V
V
DD1
, V
DD2
– 0.4
0.2
0.4
V
I
Ox
= +4 mA, V
Ix
= V
IxL
30
5
2.5
35
100
50
5
30
5
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
kV/μs
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
V
IA
, V
IB
, V
IC
, V
ID
= 0 or V
DD1
V
IA
, V
IB
, V
IC
, V
ID
= 0 or V
DD1
mA/Mbps
mA/Mbps
|CM
H
|
25
|CM
L
|
25
35
kV/μs
1.1
0.10
0.03
2.0
5.0
Mbps
μs
μs
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