I2CADD—I2C Address Register " />
參數(shù)資料
型號(hào): ADUC847BSZ62-5
廠商: Analog Devices Inc
文件頁數(shù): 68/108頁
文件大?。?/td> 0K
描述: IC FLASH MCU W/24BIT ADC 52-MQFP
產(chǎn)品培訓(xùn)模塊: Process Control
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 62KB(62K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x24b; D/A 1x12b,2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 52-QFP
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
配用: EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 62 of 108
I2CADD—I2C Address Register 1
Function:
Holds one of the I2C peripheral addresses for the part. It may be overwritten by user code. Application
Note uC001 at http://www.analog.com/microconverter describes the format of the I2C standard 7-bit address.
SFR Address:
9BH
Power-On Default:
55H
Bit Addressable:
No
I2CADD1—I2C Address Register 2
Function:
Same as the I2CADD.
SFR Address:
F2H
Power-On Default:
7FH
Bit Addressable:
No
I2CDAT—I2C Data Register
Function:
The I2CDAT SFR is written to by user code to transmit data, or read by user code to read data just received by
the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the
I2CCON SFR. User code should access I2CDAT only once per interrupt cycle.
SFR Address:
9AH
Power-On Default:
00H
Bit Addressable:
No
The main features of the MicroConverter I2C interface are
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I2C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit
address, single master/slave relationships can exist at all
times even in a multislave environment.
The ability to respond to two separate addresses when
operating in slave mode.
On-chip filtering rejects <50 ns spikes on the SDATA and
the SCLOCK lines to preserve data integrity.
DVDD
I2C
MASTER
I2C
SLAVE 1
I2C
SLAVE 2
04741-045
Figure 45. Typical I2C System
Software Master Mode
The ADuC845/ADuC847/ADuC848 can be used as an I2C
master device by configuring the I2C peripheral in master mode
and writing software to output the data bit-by-bit. This is
referred to as a software master. Master mode is enabled by
setting the I2CM bit in the I2CCON register.
To transmit data on the SDATA line, MDE must be set to enable
the output driver on the SDATA pin. If MDE is set, the SDATA
pin is pulled high or low depending on whether the MDO bit is
set or cleared. MCO controls the SCLOCK pin and is always
configured as an output in master mode. In master mode, the
SCLOCK pin is pulled high or low depending on the whether
MCO is set or cleared.
To receive data, MDE must be cleared to disable the output
driver on SDATA. Software must provide the clocks by toggling
the MCO bit and reading the SDATA pin via the MDI bit. If
MDE is cleared, MDI can be used to read the SDATA pin. The
value of the SDATA pin is latched into MDI on a rising edge of
SCLOCK. MDI is set if the SDATA pin is high on the last rising
edge of SCLOCK. MDI is cleared if the SDATA pin is low on the
last rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to
generate the start condition, slave address, acknowledge bits,
data bytes, and stop conditions. These functions are described
in Application Note uC001.
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