參數(shù)資料
型號: ADUC841BCPZ62-5
廠商: Analog Devices Inc
文件頁數(shù): 58/88頁
文件大?。?/td> 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設備: DMA,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
配用: EVAL-ADUC841QSZ-ND - KIT DEV FOR ADUC841 QUICK START
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 61 of 88
TCON
Timer/Counter 0 and 1
Control Register
SFR Address
88H
Power-On Default
00H
Bit Addressable
Yes
Table 29. TCON SFR Bit Designations
Bit No.
Name
Description
7
TF1
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
6
TR1
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
5
TF0
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
4
TR0
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
3
IE11
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT1, depending on
the state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip
hardware.
2
IT11
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, i.e., 1-to-0 transition.
Cleared by software to specify level-sensitive detection, i.e., zero level.
1
IE01
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or by a zero level being applied to external interrupt pin INT0, depending on the
state of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip
hardware.
0
IT01
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, i.e.,1-to-0 transition.
Cleared by software to specify level-sensitive detection, i.e., zero level.
1These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as
independent registers or combined into a single 16-bit register
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH, respectively.
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