參數(shù)資料
型號(hào)： ADUC832BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/92頁(yè)
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
包裝： 托盤(pán)
Data Sheet
ADuC832
Rev. B | Page 51 of 92
USER INTERFACE TO OTHER ON-CHIP ADUC832 PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC832 incorporates two 12-bit voltage output DACs on
chip. Each DAC has a rail-to-rail voltage output buffer capable
of driving 10 k/100 pF. Each has two selectable ranges, 0 V to
VREF (the internal band gap 2.5 V reference) and 0 V to AVDD.
Each can operate in 12-bit or 8-bit mode. Both DACs share a
control register, DACCON, and four data registers, DAC1H,
DAC1L, DAC0H, and DAC0L. Note that in 12-bit asynchron-
ous mode, the DAC voltage output is updated as soon as the
DACL data SFR has been written; therefore, the DAC data
registers should be updated as DACH first, followed by DACL.
Note that for correct DAC operation on the 0 V to VREF range,
the ADC must be switched on. This results in the DAC using
the correct reference value.
DACCON (DAC Control Register)
SFR Address:
FDH
Power-On Default Value:
04H
Bit Addressable:
No
DACxH/DACxL (DAC Data Registers)
Function:
DAC data registers, written by user to
update the DAC output
SFR Address:
DAC0L (DAC0 data low byte) = F9H;
DAC1L (DAC1 data low byte) = FBH
DAC0H (DAC0 data high byte) = FAH;
DAC1H (DAC1 data high byte) = FCH
Power-On Default
Value:
00H (all four registers)
Bit Addressable:
No (all four registers)
The 12-bit DAC data should be written into DACxH/DACxL
right-justified such that DACxL contains the lower eight bits,
and the lower nibble of DACxH contains the upper four bits.
Table 25. DACCON SFR Bit Designations
Bit
Name
Description
[7]
Mode
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to 1 = 8-bit mode (write eight bits to DACxL SFR).
Set to 0 = 12-bit mode.
[6]
RNG1
DAC1 range select bit.
Set to 1 = DAC1 range 0 V VDD.
Set to 0 = DAC1 range 0 V VREF.
[5]
RNG0
DAC0 range select bit.
Set to 1 = DAC0 range 0 V VDD.
Set to 0 = DAC0 range 0 V VREF.
[4]
CLR1
DAC1 clear bit.
Set to 0 = DAC1 output forced to 0 V.
Set to 1 = DAC1 output normal.
[3]
CLR0
DAC0 clear bit. Set to 0 = DAC1 Output Forced to 0 V. Set to 1 = DAC1 output normal.
[2]
SYNC
DAC0/DAC1 update synchronization bit.
When set to 1, the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update
both DACs by first updating the DACxL/DACxH SFRs while SYNC is 0. Both DACs then update simultaneously
when the SYNC bit is set to 1.
[1]
PD1
DAC1 Power-down bit.
Set to 1 = power on DAC1.
Set to 0 = power off DAC1.
[0]
PD0
DAC0 Power-Down Bit.
Set to 1 = power on DAC0.
Set to 0 = power off DAC0.
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