參數(shù)資料
型號(hào): ADUC824
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU
中文描述: MicroConverter的,雙通道ADC的16-/24-Bit與嵌入式閃存MCU
文件頁(yè)數(shù): 8/68頁(yè)
文件大小: 1060K
代理商: ADUC824
REV. B
ADuC824
TIMING SPECIFICATIONS
1, 2, 3
(AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V;
all specifications T
MIN
to T
MAX
unless otherwise noted.)
–8–
32.768 kHz External Crystal
Min
Typ
Parameter
Max
Unit
Figure
CLOCK INPUT (External Clock Driven XTAL1)
t
CK
XTAL1 Period
t
CKL
XTAL1 Width Low
t
CKH
XTAL1 Width High
t
CKR
XTAL1 Rise Time
t
CKF
XTAL1 Fall Time
1/t
CORE
ADuC824 Core Clock Frequency
4
t
CORE
ADuC824 Core Clock Period
5
t
CYC
ADuC824 Machine Cycle Time
6
30.52
15.24
15.24
20
20
μ
s
μ
s
μ
s
ns
ns
MHz
μ
s
μ
s
1
1
1
1
1
0.098
12.58
0.636
7.6
0.95
122.45
NOTES
1
AC inputs during testing are driven at DV
DD
– 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V
IH
min for a Logic 1 and V
IL
max for
a Logic 0 as shown in Figure 2.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V
OH
/V
OL
level occurs as shown in Figure 2.
3
C
LOAD
for Port0, ALE,
PSEN
outputs = 100 pF; C
LOAD
for all other outputs = 80 pF unless otherwise noted.
4
ADuC824 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
6
ADuC824 Machine Cycle Time is nominally defined as 12/Core_CLK.
t
CHK
t
CKL
t
CK
t
CKF
t
CKR
Figure 1. XTAL1 Input
DV
DD
0.5V
0.45V
0.2DV
+ 0.9V
TEST POINTS
0.2DV
DD
0.1V
V
LOAD
0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
0.1V
V
LOAD
V
LOAD
+ 0.1V
Figure 2. Timing Waveform Characteristics
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