參數(shù)資料
型號(hào)： ADUC702X
廠(chǎng)商： Analog Devices, Inc.
元件分類(lèi)： 32位微控制器
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 60/80頁(yè)
文件大小： 840K
代理商： ADUC702X
ADuC702x Series
Preliminary Technical Data
3
Rev. PrB | Page 60 of 80
General call enable bit
Set
by user to address every device on the I
2
C bus
Cleared
by user to operate in normal mode
Reserved
Master enable bit
Set
by user to enable the master I
2
C channel
Cleared
by user to disable the master I
2
C channel
Slave enable bit
Set
by user to enable the slave I
2
C channel. A slave transfer sequence will be monitored for the device address in I2C0ID0,
I2C0ID1, I2C0ID2 and I2C0ID3. if the device address is recognised the part will participate in the slave transfer sequence
Cleared
by user to disable the slave I
2
C channel
2
1
0
Table 49: I2C0SSTA MMR Bit Descriptions
Bit
7
Description
Transmit FIFO flush
Set
by user to flush the transmit FIFO
Cleared
by user to operate in normal mode
Slave busy
Set
automatically if the slave is busy
Cleared
automatically
No ACK
Set
if master asking for data and no data is available
Cleared
automatically
Slave receive FIFO overflow
Set
automatically if the slave receive FIFO is overflowing
Cleared
automatically by reading I2C0SRX
Slave receive IRQ
Set
after receiving data
Cleared
automatically by reading the I2C0SRX register
Slave transmit IRQ
Set
at the end of a transmission
Cleared
automatically by writing to the I2C0STX register
Slave transmit FIFO underflow
Set
automatically if the slave transmit FIFO is underflowing
Cleared
automatically by writing to the I2C0STX register
Slave transmit FIFO empty
Set
automatically if the slave transmit FIFO is empty
Cleared
automatically by writing to the I2C0STX register
6
5
4
3
2
1
0
Table 50: I2C0MSTA MMR Bit Descriptions
Bit
7
Description
Transmit FIFO flush
Set
by user to flush the transmit FIFO
Cleared
by user to operate in normal mode
Master busy
Set
automatically if the master is busy
Cleared
automatically
Arbitration loss
Set
in multi-master mode if another master has the bus
Cleared
when the bus becomes available
6
5
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