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參數資料
| 型號： | ADUC702X |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數： | 39/80頁 |
| 文件大小： | 840K |
| 代理商： | ADUC702X |
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Preliminary Technical Data
ADuC702x Series
POWER SUPPLY MONITOR
Rev. PrB | Page 39 of 80
The Power Supply Monitor monitors the IOV
DD
supply on the
ADuC702x. It indicate when IOV
DD
supply pin drops below one
of two supply trip points. The monitor function is controlled via
the PSMCON register. If enabled in the IRQEN or FIQEN
register, the monitor will interrupt the core using the PSMI bit
in the PSMCON MMR. This bit will be cleared immediately
once CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brown-out
conditions, and also ensures that normal code execution will
not resume until a safe supply level has been established.
Table 21: PSMCON MMR bit descriptions
Bit
3
Name
CMP
Description
Comparator Bit
This is a read-only bit and directly reflects the state of the comparator
Read ‘1’ indicates the IOV
DD
supply is above its selected trip point.
Read ‘0’ indicates the IOV
DD
supply is below its selected trip point.
Trip Point Selection Bits
0 - 2.79V
1 - 3.07V
Power Supply Monitor Enable Bit
Set
to ‘1’ by the user to enable the Power Supply Monitor circuit
Clear
to ‘0’ by the user to disable the Power Supply Monitor circuit
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if CMP is low, indicating low I/O supply. The PSMI Bit
can be used to interrupt the processor. Once CMP
returns high, the PSMI bit may be cleared by writing
a ‘1’ to this location. A write of ‘0’ has no effect. There is no timeout delay, PSMI may be cleared
immediately once CMP goes high.
2
TP
1
PSMEN
0
PSMI
COMPARATOR
The ADuC702x also integrates an uncommitted voltage
comparator.
The positive input is multiplexed with ADC2 and the negative
input has two options: ADC3 or DAC0. The output of the
comparator can be configured to generate a system interrupt,
can be routed directly to the Programmable Logic Array, can
start an ADC conversion or be on an external pin, CMP
OUT
.
MUX
ADC2/CMP0
ADC3/CMP1
DAC0
IRQ
ADC START
CONVERSION
PLA
P0.0/CMP
OUT
MUX
Figure 19: Comparator
The comparator interface consists on a 16-bit MMR, CMPCON
described below.
Table 22: CMPCON MMR bit descriptions
Bit
15-11
10
Name
CMPEN
Description
Reserved
Comparator enable bit:
Set
by user to enable the comparator
Cleared
by user to disable the comparator
Comparator negative input select bits:
00
Reserved
01
ADC3 input
9-8
CMPIN
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