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| 型號： | ADSQ-1410-EX-C |
| 廠商： | MURATA POWER SOLUTIONS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DMA66 |
| 封裝： | ROHS COMPLIANT, SMT-66 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 432K |
| 代理商： | ADSQ-1410-EX-C |
ADSQ-1410
Quad 14-Bit, 10 MSPS Sampling A/D Converter
DATEL
11 Cabot Boulevard, Manseld, MA 02048-1151 USA
Tel: (508) 339-3000
www.datel.com
e-mail: help@datel.com
01 Apr 2011
MDA_ADSQ.B02 Page 7 of 11
INPUT (A, C, D, B) - Pins 1, 7, 28, 33: Analog Input Signal for respective
channels.
SGND (A, C, D, B) - Pins 2, 8, 27, 32: Signal ground for respective chan-
nels. SGND connected to AGND and DGND at strategic locations within the
ADSQ-1410.
OFFSET ADJ (A, C, D, B) - Pins 3, 9, 26, 31: Provides independent offset
adjustment for each channel. Designed for ± voltages applied to OFFSET
ADJ pin; leave oating or tied to GND for non-adjustment applications. Apply-
ing -1V reduces output by approx. 76 codes; applying +1.0V increases output
by approx. 76 codes with RANGE = 2.5V.
+5V (A, C, D, B) - Pins 4, 10, 25, 30: Individual +5V analog supply pins for
each channel. Bypass to respective AGND pins with 1uF and 0.1uF ceramic
capacitors.
-5V (AB, CD) - Pins 5, 11: Individual -5V analog supply pins for each chan-
nel. Bypass to respective AGND pins with 1uF and 0.1uF ceramic capacitors.
AGND (A, C, D, B) - Pins 6, 12, 24, 29: Analog ground (+5V and -5V returns)
for respective channels. AGND connected to SGND and DGND at strategic
locations within the ADSQ-1410.
RANGE (A, B, C, D) - Pin 13, 15, 16, 17: Used with +2.5V REF to select the
respective channel's full scale input range and ne gain adjustment. See
Range and Calibration section.
+2.5V REF - Pin 14: Precision +2.5V output voltage used with RANGE to
select full scale input range for all channels. See Range and Calibration sec-
tion. Bypass to AGND Plane.
PIN FUNCTIONS
Pin Number Name
Description
1, 7, 28, 33
INPUT (A, C, D, B)
Signal Input for Respective Channel
2, 8, 27, 32
SGND (A, C, D, B)
Signal Ground for Respective Channel
3, 9, 26, 31
OFFSET ADJ (A, C, D, B) Offset Adjust for Respective Channel
4, 10, 25, 30
+5V (A, C, D, B)
+5V Analog Supply for Respective Channel
5, 11
-5V (A, C, D, B)
-5V Analog Supply for Respective Channel
6, 12, 24, 29
AGND (AB, CD)
Analog Ground for Respective Channel
13
RANGE_A
Channel A Range Adjustment
14
+2.5V REF
+2.5V Reference Output Voltage
15
Range_C
Channel C Range Adjustment
16
Range D
Channel D Range Adjustment
17
Range B
Channel B Range Adjustment
18, 23
OGND_AB
Digital Ground for Respective Channel
19, 22
+VDD (AB, CD)
Output Supply for Respective Channel
34-47
DATA OUT_CD
Data Output Bits for Channels C&D
21
Overow_CD
Overow/Underow for Channels C&D
48
EN_B
Output Enable Channel B
49
EN_D
Output Enable Channel D
50
START CONV
Start Convert for all Channels
51
EN_C
Output Enable Channel C
52
EN_A
Output Enable Channel A
53-66
DATA OUT_AB
Data Output Bits for Channels A&B
20
Overow_AB
Overow/Underow for Channels A&B
Table 3. Pin Function Description
PIN FUNCTIONS, CONT.
+VDD (AB, CD) - Pins 19, 22: Supply voltage for digital circuitry. Chan-
nels AB share common supply pin, channels CD share common supply pin.
Bypass to respective OGND pins with 1uF and 0.1uF ceramic capacitors.
OGND (AB, CD) - Pins 18, 23: Output ground (OGND_AB and OGND_CD
returns) for associated channels. OGND is connected to AGND and other
OGND at strategic locations within the ADSQ-1410.
DATA_OUT_CD – Pins 34 – 47: Digital data from channels C&D are buffered
internally, with the capability of selecting between active and High-Z states,
and brought out on the DATA_OUT_CD pins. Selection between C or D is con-
trolled by EN_C and EN_D control pins. DATA OUT employs the offset binary
coding format and is powered from +VDD_CD supply.
OVERFLOW_CD - Pin 21: Overow is a digital output that is multiplexed onto
the output data bus in the same manner as the data bits and is enabled or
inactive (High-Z) along with the corresponding) data outputs (same latency
delay via the respective EN control pin. The signal is LO when the data is
within the valid input range of the corresponding A/D converter and HI when
the input signal is: +FS-1/2LSB <input> -FS-1/2LSB.
EN_C - Pin 51: Control pin for channel C output data. The data output for
channel C is buffered internally with the capability to select between active
and High-Z states. The channel C data output shares pins with channel D
(DATA_OUT_CD). Caution must be exercised to assure that channel C and
channel D are not enabled at the same time. A LO enables the corresponding
channel's output data; a HI places the channel into a High-Z state.
EN_D - Pin 49: Control pin for channel D output data. The data output for
channel D is buffered internally with the capability to select between active
and High-Z states. The channel D data output shares pins with channel C
(DATA_OUT_CD). Caution must be exercised to assure that channel D and
channel C are not enabled at the same time.
DATA_OUT_AB – Pins 53 – 66: Digital data from channels A&B are buffered
internally, with the capability of selecting between active and High-Z states,
and brought out on the DATA_OUT_AB pins. Selection between A or B is
controlled by EN_A and EN_B control pins. DATA OUT employs the offset
binary coding format and is powered from +VDD_AB supply. A LO enables
the corresponding channel's output data; a HI places the channel into a
High-Z state.
OVERFLOW_AB - Pin 20: Overow is a digital output that is multiplexed onto
the output data bus in the same manner as the data bits and is enabled or
inactive (High-Z) along with the corresponding) data outputs (same latency
delay via the respective EN control pin. The signal is LO when the data is
within the valid input range of the corresponding A/D converter and HI when
the input signal is: +FS-1/2LSB <input> -FS-1/2LSB.
EN_A - Pin 52: Control pin for channel A output data. The data output for
channel A is buffered internally with the capability to select between active
and High-Z states. The channel A data output shares pins with channel B
(DATA_OUT_AB). Caution must be exercised to assure that channel A and
channel B are not enabled at the same time. A LO enables the corresponding
channel's output data; a HI places the channel into a High-Z state.
EN_B - Pin 48: Control pin for channel B output data. The data output for
channel B is buffered internally with the capability to select between active
and High-Z states. The channel B data output shares pins with channel A
(DATA_OUT_AB). Caution must be exercised to assure that channel B and
channel A are not enabled at the same time. A LO enables the corresponding
channel's output data; a HI places the channel into a High-Z state.
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