參數(shù)資料
型號(hào): ADSQ-1410-EX-C
廠商: MURATA POWER SOLUTIONS INC
元件分類: ADC
英文描述: 4-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DMA66
封裝: ROHS COMPLIANT, SMT-66
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 432K
代理商: ADSQ-1410-EX-C
ADSQ-1410
Quad 14-Bit, 10 MSPS Sampling A/D Converter
DATEL
11 Cabot Boulevard, Manseld, MA 02048-1151 USA
Tel: (508) 339-3000
www.datel.com
e-mail: help@datel.com
01 Apr 2011
MDA_ADSQ.B02 Page 4 of 11
OFFSET ADJ
20.5k
To A/D
Input
Section
SGND
VIN ±2.5V
470
ADSQ-1410 Quad Input Stage
DIGITAL OUTPUT AND TIMING
The ADSQ-1410 is congured such that the output bits and overow for
channels A&B are multiplexed on the AB Output Bus (pins 54 - 66 & 20)
and channels C&D are similarly multiplexed on the CD Output Bus (pins
34-47 & 21). See the Output Block Diagram gure. The output drivers are
designed to conveniently operate from VDD = +2V to +5V and are capable
of sinking and sourcing up to 4mA of current. However, switching large
drive currents can cause glitches on the supplies that could couple into
and create disturbances on an ongoing A/D conversion affecting the SINAD
and SNR performance. Applications where high drive current is required
may require additional supply voltage bypassing or external digital buffers.
The EN_ pins are used to select the appropriate output data. EN_ control
pins are active LO (HI= high-z). Caution must be exercised to assure that
both channels on the same bus are not enabled at the same time. Each
data bus of the ADSQ-1410 is capable of providing data throughput at a
20MHz rate. See Enable and Disable timing diagrams and table.
Input logic levels for EN_ pins are dictated by +VDD supply voltage; logic
level for START_CONV is a function of +5V supply. See Functional Speci-
cations: Digital Inputs.
Where: RANGE = the RANGE pin voltage
Codes = Desired offset adjustment range
Rexternal = External Offset series resistor
(Rexternal + 20500)
Voffset =
487.9
2 Range (Codes)
Eq. 4:
For applications that require small full scale input ranges less sensitiv-
ity may be required for offset adjustment. In this case an external series
resistor can be added with the internal 20.5kΩ resistor on the OFFSET ADJ
pin. In this case the Offset Voltage can be calculated by:
NOTE: Outputs are enabled when ENABLE pins = LO (Hi-Z = HI). Caution must
be taken to assure that shared outputs are not enabled at the same time.
DATA
OUTPUT
t
Data N-3
Data N-2
Data N-1
Data N
C
tCH
tCL
tOD
START
CONV
ANALOG
INPUT
NN + 1
N + 2
(Enable Pin = LO)
ADSQ-1410 Timing Diagram
Parameter
Symbol
Typ
Max
Hi-Z to Active HI
t-pZH
6.6ns
10.6ns
Hi-Z to Active LO
t-pZL
6.6ns
10.6ns
Active HI to Hi-Z
t-pHZ
7.8ns
11.5ns
Active LO to Hi-Z
t-pLZ
7.8ns
11.5ns
Table 2. Enable and Disable Times
Parameter
Symbol
Min
Typ
Max
Unit
Start Conv Period
tc
100
1x106
ns
Start Conv Pulse High
tch
45
ns
Start Conv Pulse Low
tcl
45
ns
Output Delay
tod
13
18
27
ns
Table 1. Digital Output And Timing
Typical for AB & CD Output Bus
EN_B
EN_A
AB Output Bus &
Overow
(pins 54-66 & 20)
A/D_ A
A/D_ B
Buffer_A
Buffer_B
Output Block Diagram
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