- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19388 > ADSP-BF537BBCZ-5B (Analog Devices Inc)IC DSP CTLR 16BIT 208CSPBGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-BF537BBCZ-5B |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 208CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | CAN，SPI，SSP，TWI，UART |
| 時(shí)鐘速率： | 500MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 132kB |
| 電壓 - 輸入/輸出： | 2.50V，3.30V |
| 電壓 - 核心： | 1.26V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 208-CSPBGA |
| 包裝： | 托盤 |
| 配用： | ADZS-BF537-ASKIT-ND - BOARD EVAL SKIT ADSP-BF537 ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BF537-EZLITE-ND - BOARD EVAL ADSP-BF537 ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT ADZS-BF537-STAMP-ND - SYSTEM DEV FOR ADSP-BF537 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Rev. J
|
Page 16 of 68
|
February 2014
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
The maximum CCLK frequency not only depends on the part’s
speed grade (see Ordering Guide on Page 67), it also depends on
on Page 24 for details). The maximal system clock rate (SCLK)
depends on the chip package and the applied VDDEXT voltage (see
BOOTING MODES
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six
mechanisms (listed in Table 8) for automatically loading inter-
nal and external memory after a reset. A seventh mode is
provided to execute from external memory, bypassing the boot
sequence.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
Boot from 8-bit and 16-bit external flash memory – The
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory
bank 0. All configuration settings are set for the slowest
device possible (3-cycle hold time; 15-cycle R/W access
times; 4-cycle setup). The Boot ROM evaluates the first
byte of the boot stream at address 0x2000 0000. If it is 0x40,
8-bit boot is performed. A 0x60 byte assumes a 16-bit
memory device and performs 8-bit DMA. A 0x20 byte also
assumes 16-bit memory but performs 16-bit DMA.
Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash
devices from
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
Boot from SPI host device – The Blackfin processor oper-
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
Boot from UART – Using an autobaud handshake
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects an “@” (boot stream) character
(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD
pin to determine the bit rate. It then replies with an
acknowledgement that is composed of 4 bytes: 0xBF, the
value of UART_DLL, the value of UART_DLH, and 0x00.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS.
Therefore, the host must monitor this signal.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO:SCLK
Example Frequency Ratios
(MHz)
VCO
SCLK
0001
1:1
100
0110
6:1
300
50
1010
10:1
500
50
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO:CCLK
Example Frequency Ratios
(MHz)
VCO
CCLK
00
1:1
300
01
2:1
300
150
10
4:1
500
125
11
8:1
200
25
Table 8. Booting Modes
BMODE2– 0
Description
000
Execute from 16-bit external memory (bypass
boot ROM)
001
Boot from 8-bit or 16-bit memory
(EPROM/flash)
010
Reserved
011
Boot from serial SPI memory (EEPROM/flash)
100
Boot from SPI host (slave mode)
101
Boot from serial TWI memory (EEPROM/flash)
110
Boot from TWI host (slave mode)
111
Boot from UART host (slave mode)
Table 8. Booting Modes (Continued)
BMODE2–0
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-BF534YBCZ-4B | IC DSP CTLR 16BIT 400MHZ 208-CSP |
| ADSP-21488BSWZ-3A | IC DSP 3MBIT 400MHZ 100LQFP |
| ADSP-BF544MBBCZ-5M | IC DSP 16BIT 533MHZ MDDR 400CBGA |
| SWS600L-5 | POWER SUPPLY 5V 120A SGL OUTPUT |
| ADSP-BF544BBCZ-5A | IC DSP 16BIT 533MHZ 400CSBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF537BBCZ-5BV | 功能描述:IC DSP CTLR 16BIT 208CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF537BBCZ5BVX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF537BBCZ-5BX | 制造商:Analog Devices 功能描述:208-MEG PB FREE SPARSE - Trays |
| ADSP-BF537KBC-6A | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 600MHZ 600MIPS 182CSPBGA - Trays |
| ADSP-BF537KBCZ-6A | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 600MHz 600MIPS 182-Pin CSP-BGA 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。