參數(shù)資料
型號(hào)： ADSP-BF536BBC-4A
廠商： Analog Devices Inc
文件頁數(shù)： 3/68頁
文件大?。?/td> 0K
描述： IC DSP CTLR 16BIT 182CSPBGA
產(chǎn)品培訓(xùn)模塊： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，SPI，SSP，TWI，UART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 外部
芯片上RAM： 100kB
電壓 - 輸入/輸出： 2.50V，3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 182-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 182-CSPBGA（12x12）
包裝： 托盤
Rev. J
|
Page 11 of 68
|
February 2014
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA
) serial infrared
physical layer link specification (SIR) protocol.
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer
a CAN controller that is a communication controller imple-
menting the CAN 2.0B (active) protocol. This protocol is an
asynchronous communications protocol used in both industrial
and automotive control systems. The CAN protocol is well-
suited for control applications due to its capability to communi-
cate reliably over a network, since the protocol incorporates
CRC checking message error tracking, and fault node
confinement.
The CAN controller offers the following features:
32 mailboxes (eight receive only, eight transmit only, 16
configurable for receive or transmit).
Dedicated acceptance masks for each mailbox.
Additional data filtering on first two bytes.
Support for both the standard (11-bit) and extended
(29-bit) identifier (ID) message formats.
Support for remote frames.
Active or passive network support.
CAN wake-up from hibernation mode (lowest static power
consumption mode).
Interrupts, including: Tx complete, Rx complete, error,
global.
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
CAN module represents only the controller part of the interface.
The controller interface supports connection to 3.3 V high-
speed, fault-tolerant, single-wire transceivers.
TWI CONTROLLER INTERFACE
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
include a 2-wire interface (TWI) module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I2C
bus standard. The
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two pins for
transferring clock (SCL) and data (SDA) and supports the
protocol at speeds up to 400 kbps. The TWI interface pins are
compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
10/100 ETHERNET MAC
The ADSP-BF536 and ADSP-BF537 processors offer the capa-
bility to directly connect to a network by way of an embedded
fast Ethernet Media Access Controller (MAC) that supports
both 10-BaseT (10 Mbps) and 100-BaseT (100 Mbps) operation.
The 10/100 Ethernet MAC peripheral is fully compliant to the
IEEE 802.3-2002 standard, and it provides programmable fea-
tures designed to minimize supervision, bus use, or message
processing by the rest of the processor system.
Some standard features are
Support of MII and RMII protocols for external PHYs.
Full duplex and half duplex modes.
Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS.
Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing.
Flow control (in full-duplex operation): generation and
detection of PAUSE frames.
Station management: generation of MDC/MDIO frames
for read-write access to PHY registers.
SCLK operating range down to 25 MHz (active and sleep
operating modes).
Internal loopback from Tx to Rx.
Some advanced features are
Buffered crystal output to external PHY for support of a
single crystal system.
Automatic checksum computation of IP header and IP
payload fields of Rx frames.
Independent 32-bit descriptor-driven Rx and Tx DMA
channels.
Frame status delivery to memory via DMA, including
frame completion semaphores, for efficient buffer queue
management in software.
Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations.
Convenient frame alignment modes support even 32-bit
alignment of encapsulated Rx or Tx IP packet data in mem-
ory after the 14-byte MAC header.
Programmable Ethernet event interrupt supports any com-
bination of
Any selected Rx or Tx frame status conditions.
PHY interrupt condition.
Wake-up frame detected.
Any selected MAC management counter(s) at
half-full.
DMA descriptor error.
47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value.
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