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參數(shù)資料
| 型號： | ADSP-BF536BBC-3A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 48/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 182CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | CAN，SPI，SSP，TWI，UART |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 100kB |
| 電壓 - 輸入/輸出： | 2.50V，3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 182-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 182-CSPBGA（12x12） |
| 包裝： | 托盤 |
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Rev. J
|
Page 52 of 68
|
February 2014
TEST CONDITIONS
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Figure 48 shows the measurement point for ac measurements
(other than output enable/disable). The measurement point is
VMEAS = VDDEXT/2.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 49). The time tENA_MEA-
SURED is the interval from when the reference signal switches to
when the output voltage reaches 2.0 V (output high) or 1.0 V
(output low). Time tTRIP is the interval from when the output
starts driving to when the output reaches the 1.0 V or 2.0 V trip
voltage. Time tENA is calculated as shown in
the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by
the equation:
The output disable time tDIS is the difference between tDIS_MEA-
the interval from when the reference signal switches to when the
output voltage decays V from the measured output-high or
output-low voltage. The time tDECAY is calculated with the test
loads CL and IL, and with V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical V is 0.4 V. CL is the total bus capacitance (per data line),
and IL is the total leakage or three-state current (per data line).
The hold time is tDECAY plus the minimum disable time (for
example, tDSDAT for an SDRAM write cycle).
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
INPUT
OR
OUTPUT
VMEAS
tENA
tENA_MEASURED tTRIP
–
=
Figure 49. Output Enable/Disable
tDECAY
CL V
I
L
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
VOH (MEASURED)
V
VOL (MEASURED) + V
tDIS_MEASURED
VOH
(MEASURED)
VOL
(MEASURED)
VTRIP(HIGH)
VOH(MEASURED)
VOL(MEASURED)
HIGH IMPEDANCE STATE
OUTPUT STOPS DRIVING
tENA
tDECAY
tENA_MEASURED
tTRIP
VTRIP(LOW)
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| ADSP-BF536BBC-4A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF536BBCZ-3A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF536BBCZ-3AX | 制造商:Analog Devices 功能描述:182-MBGA PB-FREE - Trays |
| ADSP-BF536BBCZ-3B | 功能描述:IC DSP CTLR 16BIT 208CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF536BBCZ3BRL | 功能描述:IC DSP CTLR 16BIT 208BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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