參數(shù)資料
型號(hào): ADSP-21msp58
廠商: Analog Devices, Inc.
英文描述: DSP Microcomputer(DSP 微計(jì)算機(jī))
中文描述: 微機(jī)的DSP(數(shù)字信號(hào)處理器微計(jì)算機(jī))
文件頁數(shù): 25/40頁
文件大?。?/td> 392K
代理商: ADSP-21MSP58
ADSP-21msp58/59
REV. 0
–25–
Parameter
Min
Max
Unit
Clock Signals
t
CK
is defined as 0.5 t
CK I.
T he ADSP-21msp58/59 uses
an input clock with a quency equal to half the instruction
rate; a 13 MHz input clock (which is equivalent to 76.92 ns)
yields a 38.46 ns processor cycle (equivalent to 26 MHz).
t
CK
values within the range of 0.5 t
CK I
period should be
substituted for all relevant timing parameters to obtain
specification value. Example: t
CK H
= 0.5t
CK
– 7 ns
= 0.5 (38.46 ns) – 7 ns = 12.23 ns.
T iming Requirement:
t
CK I
CLK IN Period
t
CK IL
CLK IN Width Low
t
CK IH
CLK IN Width High
76.92
20
20
125
ns
ns
ns
Switching Characteristic:
t
CK L
t
CK H
t
CK OH
Control Signals
T iming Requirement:
t
RSP
CLK OUT Width Low
CLK OUT Width High
CLK IN High to CLK OUT High
0.5t
CK
– 7
0.5t
CK
– 7
0
ns
ns
ns
20
RESET
Width Low
5t
CK1
ns
NOT ES
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLK IN cycles assuming stable CLK IN (not including
crystal oscillator start-up time).
CLKIN
t
CKIL
t
CKIH
t
CKI
t
CKOH
t
CKH
t
CKL
CLKOUT
Figure 15. Clock Signals
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