參數(shù)資料
型號: ADSP-2191MBST-140
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 30/52頁
文件大?。?/td> 1873K
代理商: ADSP-2191MBST-140
ADSP-2191M
–30–
REV. 0
Host Port ALE Mode Read Cycle Timing
Table 17
and
Figure 16
describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK,
Ready, ALE, and ACC mode selection, see the Host port modes description
on page 8
.
Table 17. Host Port ALE Mode Read Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
t
RHKS1
t
RHKS2
t
RHKH
t
RHS
t
RHH
HRD
Asserted to HACK Asserted (ACK Mode) First Byte
HRD
Asserted to HACK Asserted (Setup, ACK Mode)
2
HRD
Deasserted to HACK Deasserted (Hold, ACK Mode)
HRD
Asserted to HACK Asserted (Setup, Ready Mode)
HRD
Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
HRD
Deasserted to Data Invalid (Hold)
HRD
Deasserted to Data Disable
12t
HCLK
15t
HCLK
+t
NH1
12
10
10
15t
HCLK
+t
NH1
1
t
NH
are peripheral bus latencies (n
the same time.
2
Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
t
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
ns
ns
ns
ns
ns
12t
HCLK
t
RDH
t
RDD
1
ns
ns
10
Timing Requirements
t
CSAL
t
ALCS
HCMS
or
HCIOMS
Asserted to HALE Asserted (Delay)
HALE Deasserted to Optional
HCMS
or
HCIOMS
Deasserted
HRD
Deasserted to
HCMS
or
HCIOMS
Deasserted
HALE Deasserted to
HRD
Asserted
HRD
Deasserted (After Last Byte) to
HCMS
or
HCIOMS
Deasserted (Ready for Next Read)
HALE Asserted Pulsewidth
HACK Asserted to
HRD
Deasserted (Hold, ACK Mode)
Address Valid to HALE Deasserted (Setup)
HALE Deasserted to Address Invalid (Hold)
0
1
ns
ns
t
RCSW
t
ALR
t
RCS
0
5
0
ns
ns
ns
t
ALPW
t
HKRD
t
AALS
t
ALAH
4
1.5
2
4
ns
ns
ns
ns
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