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| 型號： | ADSP-2188NBSTZ-320 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 80MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.90V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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ADSP-218xN
Rev. A
|
Page 15 of 48
|
August 2006
(BR) signal. If the ADSP-218xN is not performing an external
memory access, it responds to the active BR input in the follow-
ing processor cycle by:
Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
Asserting the bus grant (BG) signal, and
Halting program execution.
If Go Mode is enabled, the ADSP-218xN will not halt program
execution until it encounters an instruction that requires an
external memory access.
If an ADSP-218xN series member is performing an external
memory access when the external device asserts the BR signal, it
will not three-state the memory interfaces nor assert the BG sig-
nal until the processor cycle after the access completes. The
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH pin is asserted when an ADSP-218xN series member
requires the external bus for a memory or BDMA access, but is
stopped. The other device can release the bus by deasserting bus
request. Once the bus is released, the ADSP-218xN deasserts BG
and BGH and executes the external memory access.
FLAG I/O PINS
ADSP-218xN series members have eight general-purpose pro-
grammable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register is
used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the
ADSP-218xN’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
In addition to the programmable flags, ADSP-218xN series
members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2.
FL0 to FL2 are dedicated output flags. FI and FO are available as
an alternate configuration of SPORT1.
Note:
Pins PF0, PF1, PF2, and PF3 are also used for device con-
figuration during reset.
INSTRUCTION SET DESCRIPTION
The ADSP-218xN series assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the follow-
ing benefits:
The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical arith-
metic add instruction, such as AR = AX0 + AY0, resembles
a simple equation.
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be
relocated to utilize on-chip memory and conform to the
ADSP-218xN’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the condition
can be checked and the operation executed in the same
instruction cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single instruc-
tion cycle.
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware
development tools supports the ADSP-218xN series. The DSP
tools include an integrated development environment, an evalu-
ation kit, and a serial port emulator.
VisualDSP++
is an integrated development environment,
allowing for fast and easy development, debug, and deployment.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder); a linker; a
PROM-splitter utility; a cycle-accurate, instruction-level simu-
lator; a C compiler; and a C run-time library that includes DSP
and mathematical functions.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:
View mixed C and assembly code (interleaved source and
object information)
Insert break points
Set conditional breakpoints on registers, memory, and
stacks
Trace instruction execution
VisualDSP++ is a registered trademark of Analog Devices, Inc.
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