參數(shù)資料
型號(hào)： ADSP-2188NBSTZ-320
廠商： Analog Devices Inc
文件頁數(shù)： 11/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 100LQFP
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 256kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.90V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
ADSP-218xN
Rev. A
|
Page 19 of 48
|
August 2006
MEMORY INTERFACE PINS
ADSP-218xN series members can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities.
The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running. Table 10 and Table 11 list the active signals at specific
pins of the DSP during either of the two operating modes (Full
Memory or Host). A signal in one table shares a pin with a sig-
nal from the other table, with the active signal determined by
the mode that is set. For the shared pins and their alternate sig-
nals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on
TERMINATING UNUSED PINS
Table 12 shows the recommendations for terminating unused
pins.
VDDINT
4I
Internal VDD (1.8 V) Power (BGA)
VDDEXT
7I
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (BGA)
GND
20
I
Ground (BGA)
EZ-Port
9
I/O
For Emulation Use
1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2 SPORT configuration determined by the DSP System Control Register. Software configurable.
Table 9. Common-Mode Pins (Continued)
Pin Name
No. of Pins
I/O
Function
Table 10. Full Memory Mode Pins (Mode C = 0)
Pin Name
No. of Pins
I/O
Function
A13 –0
14
O
Address Output Pins for Program, Data, Byte, and I/O Spaces
D23 –0
24
I/O
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory
Addresses.)
Table 11. Host Mode Pins (Mode C = 1)
Pin Name
No. of Pins
I/O
Function
IAD15 –0
16
I/O
IDMA Port Address/Data Bus
A0
1
O
Address Pin for External I/O, Program, Data, or Byte Access1
D23 –8
16
I/O
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IWR
1I
IDMA Write Enable
IRD
1
I
IDMA Read Enable
IAL
1
I
IDMA Address Latch Pin
IS
1I
IDMA Select
IACK
1
O
IDMA Port Acknowledge Configurable in Mode D; Open Drain
1 In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
Table 12. Unused Pin Terminations
Pin Name1
I/O
3-State
(Z)2
Reset
State
Hi-Z3 Caused By
Unused Configuration
XTAL
O
Float
CLKOUT
O
Float
4
A13 –1 or
O (Z)
Hi-Z
BR, EBR
Float
IAD12 –0
I/O (Z)
Hi-Z
IS
Float
A0
O (Z)
Hi-Z
BR, EBR
Float
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