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參數(shù)資料
| 型號： | ADSP-2187L |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP（Digital Signal Processing）Microcomputer(數(shù)字信號處理控制器) |
| 中文描述： | DSP（數(shù)字信號處理），微機（數(shù)字信號處理控制器） |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 79K |
| 代理商： | ADSP-2187L |
REV. 0
ADSP-2187L
–4–
DATA
Programmable I/O Pin During
Normal Operation
TECHNICAL
Mode Select Input—Checked
Only During RESET ]
COMMON-MODE PIN DE SCRIPT IONS
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
/
# of
Pins Output
1
I
1
I
1
O
1
O
1
O
1
O
1
O
1
O
1
O
1
O
1
O
1
I
Input/
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Request
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
PF7
IRQL0
/
PF6
IRQL1
/
PF5
IRQE
/
PF4
Mode D/
I/O
I
I/O
I
I/O
I
I/O
I
1
1
1
1
PF3
I/O
Mode C/
1
I
PF2
I/O
Mode B/
1
I
PF1
I/O
Mode A/
1
I
PF0
I/O
CLK IN,
X T AL
CLK OUT
SPORT 0
SPORT 1
IRQ1:0
FI, FO
PWD
PWDACK
FL0, FL1,
FL2
VDD and
GND
EZ-Port
2
1
5
5
I
O
I/O
I/O
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
2
Power-Down Control Input
Power-Down Control Output
1
1
I
O
3
O
Output Flags
16
9
I
I/O
Power and Ground
For Emulation Use
NOT ES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to en-
able the corresponding interrupts, then the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
Memory Interface Pins
T he ADSP-2187L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. T he operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
FULL ME MORY MODE PINS (MODE C = 0)
Pin
Name(s) Pins Output
A13:0
14
# of
Input/
Function
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
O
D23:0
24
I/O
HOST MODE PINS (MODE C = 1)
Pin
Name(s) Pins Output
IAD15:0 16
A0
1
# of
Input/
Function
IDMA Port Address/Data Bus
Address Pin for External I/O, Pro-
gram, Data, or Byte access
Data I/O Pins for Program, Data
Byte and I/O spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configur-
able in Mode D; Open Drain
I/O
O
D23:8
16
I/O
IRD
IAL
IS
IACK
1
1
1
1
I
I
I
I
O
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS
,
PMS
,
DM
S, and
IOMS
signals
Interrupts
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
T he ADSP-2187L provides four dedicated external interrupt in-
put pins,
IRQ2
,
IRQL0
,
IRQL1
and
IRQE
. In addition,
SPORT 1 may be reconfigured for
IRQ0
,
IRQ1
, FLAG_IN and
FLAG_OUT , for a total of six external interrupts. T he ADSP-
2187L also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. T he interrupt levels are internally prioritized and
individually maskable (except power down and reset). T he
IRQ2
,
IRQ0
and
IRQ1
input pins can be programmed to be
either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-
sensitive and
IRQE
is edge sensitive. T he priorities and vector
addresses of all interrupts are shown in T able I.
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