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參數(shù)資料
| 型號： | ADSP-2186L |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大小： | 256K |
| 代理商： | ADSP-2186L |
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ADSP-2186L
–12–
REV. A
1k
ERESET
RESET
MODE A/PF0
ADSP-2186L
PROGRAMMABLE I/O
Figure 9. Boot Mode Circuit
See the
ADSP-2100 Family EZ-Tools
data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-2186L
pins:
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
These ADSP-2186L pins are usually connected only to the
EZ-ICE
connector in the target system. These pins have no
function except during emulation, and do not require pull-up
or pull-down resistors. The traces for these signals between
the ADSP-2186L and the connector must be kept as short as
possible, no longer than three inches.
The following pins are also used by the EZ-ICE:
BR
BG
RESET
GND
The EZ-ICE
uses the EE (emulator enable) signal to take con-
trol of the ADSP-2186L in the target system. This causes the
processor to use its
ERESET
,
EBR
and
EBG
pins instead of
the
RESET
,
BR
and
BG
pins. The
BG
output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 10. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow
enough room in your system to fit the EZ-ICE probe onto the
14-pin connector.
7
1
2
3
4
5
6
8
9
10
11
12
13
14
GND
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
KEY (NO PIN)
Figure 10. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1
×
0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE
emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM, and CM
Design Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device tim-
ing requirements and switching characteristics as specified in
this DSP’s data sheet. The performance of the EZ-ICE may ap-
proach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tions for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend-
ing on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statisti-
cally vary in switching characteristics and timing requirements
within published limits.
Restriction: All memory strobe signals on the ADSP-2186L
(
RD
,
WR
,
PMS
,
DMS
,
BMS
,
CMS
and
IOMS
) used in your
target system must have 10 k
pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE
debugging sessions. These resistors may be removed at
your option when the EZ-ICE
is not being used.
Target System Interface Signals
When the EZ-ICE
board is installed, the performance of some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE
board:
EZ-ICE
emulation introduces an 8 ns propagation delay be-
tween your target circuitry and the DSP on the
RESET
signal.
EZ-ICE
emulation introduces an 8 ns propagation delay be-
tween your target circuitry and the DSP on the
BR
signal.
EZ-ICE
emulation ignores
RESET
and
BR
when single-
stepping.
EZ-ICE
emulation ignores
RESET
and
BR
when in Emulator
Space (DSP halted).
EZ-ICE
emulation ignores the state of target
BR
in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (
BG
) is asserted
by the EZ-ICE
board’s DSP.
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