參數(shù)資料
型號： ADSP-2186MBST-266
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 33 MHz, OTHER DSP, PQFP100
封裝： METRIC, PLASTIC, TQFP-100
文件頁數(shù)： 1/40頁
文件大?。?/td> 288K
代理商： ADSP-2186MBST-266
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADSP-2186M
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
DSP
Microcomputer
FUNCTIONAL BLOCK DIAGRAM
ARITHMETIC UNITS
SHIFTER
MAC
ALU
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
8K 24 BIT
DATA
MEMORY
8K 16 BIT
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
FULL MEMORY MODE
SPORT0
SERIAL PORTS
SPORT1
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
HOST MODE
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
DAG1
DATA ADDRESS
GENERATORS
DAG2
PROGRAM
SEQUENCER
ADSP-2100 BASE
ARCHITECTURE
ICE-Port is a trademark of Analog Devices, Inc.
FEATURES
Performance
13.3 ns Instruction Cycle Time @ 2.5 V (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Integration
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words Program Memory RAM
8K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
System Interface
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port Emulator Interface Supports Debugging in
Final Systems
相關PDF資料
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相關代理商/技術參數(shù)
參數(shù)描述
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