參數(shù)資料
型號(hào)： ADSP-2185NKCAZ-320
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/48頁(yè)
文件大小： 0K
描述： IC DSP 16BIT 80MHZ 144CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 80kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.80V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-CSBGA（10x10）
包裝： 托盤
Rev. A
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Page 8 of 48
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August 2006
ADSP-218xN
Clock Signals
ADSP-218xN series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal oper-
ation. The only exception is while the processor is in the power-
down state. For additional information, refer to the ADSP-218x
DSP Hardware Reference, for detailed information on this
power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xN series members use an input clock with a fre-
quency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal instruc-
tion clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xN series members include an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
RESET
The RESET signal initiates a master reset of the ADSP-218xN.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulse-width specification (tRSP).
The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, the use of an exter-
nal Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from on-
chip program memory location 0x0000 once boot loading
completes.
POWER SUPPLIES
ADSP-218xN series members have separate power supply con-
nections for the internal (VDDINT) and external (VDDEXT) power
supplies. The internal supply must meet the 1.8 V requirement.
The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up to
3.6 V, regardless of the external supply voltage. This feature pro-
vides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V
components.
Figure 3. External Crystal Connections
CL KIN
CL KO UT
XT A L
DS P
1M
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