參數(shù)資料
型號(hào): ADSP-2171BSTZ-133
廠商: Analog Devices Inc
文件頁數(shù): 45/52頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128TQFP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
Mold Change 11/Jul/2012
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 10kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–5–
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-
cated pin; SPORT1 may be reconfigured for IRQ0, IRQ1, and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are in-
ternally prioritized and individually maskable (except power-
down and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector ad-
dresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The interrupt control register, ICNTL, allows the external in-
terrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking prece-
dence or processed sequentially.
The IFC register is a write-only register used to force and clear
interrupts generated from software.
Table II. Interrupt Priority & Interrupt Vector Addresses
Interrupt Vector
Source of Interrupt
Address (Hex)
Reset (or Power-Up with PUCR = 1)
0000
(Highest Priority)
Powerdown (Nonmaskable)
002C
IRQ2
0004
HIP Write
0008
HIP Read
000C
SPORT0 Transmit
0010
SPORT0 Receive
0014
Software Interrupt 1
0018
Software Interrupt 0
001C
SPORT1 Transmit or IRQ1
0020
SPORT1 Receive or IRQ0
0024
Timer
0028
(Lowest Priority)
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, the interrupt servicing is enabled.
Figure 2. Interrupt Registers
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
SPORT0 Transmit
SPORT0 Receive
Software 1
Software 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
INTERRUPT FORCE
INTERRUPT CLEAR
IFC
98
7654321
0
10
11
12
13
14
15
0
000
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1 = enable, 0 = disable
0
ICNTL
1 = edge
0 = level
4
321
0
10
11
12
13
14
15
98
765
43
210
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IMASK
1 = enable, 0 = disable
0
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
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