參數(shù)資料
型號(hào)： ADSP-216X
廠商： Analog Devices, Inc.
英文描述： DSP Microcomputers with ROM
中文描述： DSP的微機(jī)與光盤
文件頁(yè)數(shù)： 6/39頁(yè)
文件大?。?/td> 243K
代理商： ADSP-216X
REV. 0
ADSP-216x
–6–
CLKIN
CLKOUT
XTAL
ADSP-216x
Figure 2. External Crystal Connections
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The
RESET
signal initiates a complete reset of the ADSP-216x.
The
RESET
signal must be asserted when the chip is powered
up to assure proper initialization. If the
RESET
signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If
RESET
is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 t
CK
cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the
RESET
signal should be
held low. On any subsequent resets, the
RESET
signal must
meet the minimum pulsewidth specification, t
RSP
.
To generate the
RESET
signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
The
RESET
input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When
RESET
is released, the boot loading sequence is
performed (provided there is no pending bus request and the chip
is configured for booting, with MMAP = 0). The first instruction is
then fetched from internal program memory location 0x0000.
PIN FUNCTION DESCRIPTIONS
Pin
Name(s)
Address
Data
1
# of
Pins
14
24
Input/
Output
O
I/O
Function
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request #2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
Ground Pins
Serial Port 0 Pins (
TFS0, RFS0, DT0, DR0, SCLK0
)
Serial Port 1 Pins (
TFS1, RFS1, DT1, DR1, SCLK1
)
RESET
IRQ2
BR
2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XTAL
CLKOUT
V
DD
GND
SPORT0
SPORT1
or
Interrupts and Flags:
IRQ0
(RFS1)
IRQ1
(TFS1)
FI
(DR1)
FO
(DT1)
PWDACK
3
PWDFLAG
3
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
I
O
5
5
I/O
I/O
1
1
1
1
1
1
I
I
I
O
O
I
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
Indicates when the processor has entered power-down.
Low-to-High Transition of the Power-Down Flag. Input pin can
be used to terminate power-down.
NOTES
1
Unused data bus lines may be left floating.
2
BR
must be tied high (to V
) if not used.
3
Only on ADSP-2165/ADSP-2166.
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