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參數(shù)資料
| 型號(hào)： | ADSP-216X |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DSP Microcomputers with ROM |
| 中文描述： | DSP的微機(jī)與光盤(pán) |
| 文件頁(yè)數(shù)： | 31/39頁(yè) |
| 文件大小： | 243K |
| 代理商： | ADSP-216X |
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REV. 0
ADSP-216x
–31–
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
BUS REQUEST/BUS GRANT
10.24 MHz
Min
13.0 MHz
Min
16.67 MHz
Min
Frequency Dependency
Min
Parameter
Max
Max
Max
Max
Unit
Timing Requirements:
t
BH
BR
Hold After CLKOUT High
1
t
BS
BR
Setup Before CLKOUT Low
1
Switching Characteristics:
t
SD
CLKOUT High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable
t
SDB
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable to
BG
Low
t
SE
BG
High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable
t
SEC
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable to CLKOUT High
29.4
44.4
24.2
39.2
20.0
35.0
0.25t
CK
+ 5
0.25t
CK
+ 20
ns
ns
44.4
39.2
35.0
0.25t
CK
+ 20
ns
0
0
0
0
ns
0
0
0
0
ns
14.4
9.2
5.0
0.25t
CK
– 10
ns
NOTES
1
If
BR
meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle.
BR
requires a pulsewidth greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the
ADSP-2100 Family User’s Manual
, Third Edition,
states that, “When
BR
is recognized, the processor responds immedi-
ately by asserting
BG
during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors:
BG
is asserted in the cycle
after
BR
is recognized.
No external synchronization circuit is needed when
BR
is generated as an asynchronous signal.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BS
BR
t
BH
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BG
Figure 29. Bus Request/Grant
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-2161BP-66 | DSP Microcomputers with ROM |
| ADSP-2162BS-40 | ADSP-2100 Family DSP Microcomputers |
| ADSP-2162KP-40 | DSP Microcomputers with ROM |
| ADSP-2164KP-40 | DSP Microcomputers with ROM |
| ADSP-2165KS-100 | DSP Microcomputers with ROM |
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