參數(shù)資料
型號(hào): ADSP-2163BS-100
廠商: ANALOG DEVICES INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: 100V 1A ULTRA FAST LOW-LOSS CONTROLLED AVALANCHE RECTIFIER, SMA US1 SERIES, DO-
中文描述: 24-BIT, 25 MHz, OTHER DSP, PQFP80
封裝: METRIC, PLASTIC, QFP-80
文件頁(yè)數(shù): 29/39頁(yè)
文件大?。?/td> 243K
代理商: ADSP-2163BS-100
REV. 0
ADSP-216x
–29–
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
CLOCK SIGNALS AND RESET
Frequency
Dependency
Min
10.24 MHz
Min
13.0 MHz
Min
16.67 MHz
Min
Parameter
Max
Max
Max
Max
Unit
Timing Requirements:
t
CK
CLKIN Period
t
CKL
CLKIN Width Low
t
CKH
CLKIN Width High
t
RSP
RESET
Width Low
Switching Characteristics:
t
CPL
CLKOUT Width Low
t
CPH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
97.6
20
20
488
150
76.9
20
20
384.5
150
60.0
20
20
300
150
t
CK
20
20
5t
CK1
150
ns
ns
ns
ns
38.8
38.8
0
28.5
28.5
0
20
20
0
0.5t
CK
– 10
0.5t
CK
– 10
0
ns
ns
ns
20
20
20
20
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
CLKOUT
CLKIN
t
CPL
t
CHOK
t
CPH
t
CKL
t
CKH
t
CK
Figure 27. Clock Signals
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