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參數(shù)資料
| 型號： | ADSP-21479KCPZ-1A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/76頁 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARK 200MHZ 88LFCSP |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 200MHz |
| 非易失內存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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Rev. C
|
Page 27 of 76
|
July 2013
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 19. While no specific power-up sequencing is required
between VDD_EXT and VDD_INT, there are some considerations
that the system designs should take into account.
No power supply should be powered up for an extended
period of time (>200 ms) before another supply starts to
ramp up.
If the VDD_INT power supply comes up after VDD_EXT, any
pin, such as RESETOUT and RESET, may actually drive
momentarily until the VDD_INT rail has powered up. Systems
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
Note that during power-up, when the VDD_INT power supply
comes up after VDD_EXT, a leakage current of the order of three-
state leakage current pull-up, pull-down, may be observed on
any pin, even if that is an input only (for example, the RESET
pin), until the VDD_INT rail has powered up.
Table 19. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDD_EXT or VDD_INT On
0
ms
tIVDDEVDD
VDD_INT On Before VDD_EXT
–200
+200
ms
tCLKVDD
1
CLKIN Valid After VDD_INT and VDD_EXT Valid
0
200
ms
tCLKRST
CLKIN Valid Before RESET Deasserted
10
2
μs
tPLLRST
PLL Control Setup Before RESET Deasserted
203
μs
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
4096 × tCK + 2 × tCCLK
4, 5
1 Valid V
DD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary
from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4096 cycle count depends on tSRST specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 6. Power-Up Sequencing
tRSTVDD
tCLKVDD
tCLKRST
tCORERST
tPLLRST
VDDEXT
VDDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
tIVDDEVDD
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| ADSP-21483KSWZ-3AB | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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