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參數(shù)資料
| 型號： | ADSP-21469KBCZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 32/40BIT 400MHZ 324BGA |
| 產(chǎn)品變化通告： | Pin Function Change 08/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CSPBGA |
| 包裝： | 托盤 |
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ADSP-21469
Rev. 0
|
Page 23 of 72
|
June 2010
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 17. While no specific power-up sequencing is required
between VDD_EXT, VDD_DDR2, and VDD_INT, there are some consider-
ations that the system designs should take into account.
No power supply should be powered up for an extended
period of time (> 200 ms) before another supply starts to
ramp up.
If VDD_INT power supply comes up after VDD_EXT, any pin,
such as RESETOUT and RESET, may actually drive
momentarily until the VDD_INT rail has powered up. Systems
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
Note that during power-up, when the VDD_INT power supply
comes up after VDD_EXT, a leakage current of the order of three-
state leakage current pull-up, pull-down may be observed on
any pin, even if that pin is an input only (for example the RESET
pin) until the VDD_INT rail has powered up.
Table 17. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDD_INT or VDD_EXT or VDD_DDR2 On
0
ms
tIVDD-EVDD
VDD_INT On Before VDD_EXT
–200
+200
ms
tEVDD_DDR2VDD
VDD_EXT On Before VDD_DDR2
–200
+200
ms
tCLKVDD
1
CLKIN Valid After VDD_INT or VDD_EXT or VDD_DDR2 Valid
0
200
ms
tCLKRST
CLKIN Valid Before RESET Deasserted
102
ms
tPLLRST
PLL Control Setup Before RESET Deasserted
203
ms
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
4096 × tCK + 2 × tCCLK
4, 5
ms
1 Valid V
DD
_INT assumes that the supply is fully ramped to its nominal value. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the
design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4096 cycle count depends on tSRST specification in Table 19. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 6. Power-Up Sequencing
tRSTVDD
tCLKVDD
tCLKRST
tCORERST
tPLLRST
VDDEXT
VDDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
tIVDDEVDD
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| ADSP-21469KBCZ-4 | 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBZ-EN | 制造商:Analog Devices 功能描述: |
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