參數(shù)資料
型號(hào)： ADSP-21469KBCZ-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/72頁(yè)
文件大?。?/td> 0K
描述： IC DSP 32/40BIT 400MHZ 324BGA
產(chǎn)品變化通告： Pin Function Change 08/Mar/2012
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 外部
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 324-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 324-CSPBGA
包裝： 托盤
ADSP-21469
Rev. 0
|
Page 21 of 72
|
June 2010
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
ence levels.
In the following sections, Switching Characteristics specify how
the processor changes its signals. Circuitry external to the pro-
cessor must be designed for compatibility with these signal
characteristics. Switching characteristics describe what the pro-
cessor will do in a given circumstance. Use switching
characteristics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
In the following sections, Timing Requirements apply to signals
that are controlled by circuitry external to the processor, such as
the data input for a read operation. Timing requirements guar-
antee that the processor operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 18.
The product of CLKIN and PLLM must never exceed 1/2 of
fVCO (max) in Table 18 if the input divider is not enabled
(INDIV = 0).
The product of CLKIN and PLLM must never exceed
fVCO (max) in Table 18 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) ÷ (PLLD)
where:
fVCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = Divider value 2, 4, 8, or 16 based on the PLLD value
programmed on the PMCTL register. During reset this value
is 2.
fINPUT = input frequency to the PLL
fINPUT = CLKIN when the input divider is disabled, or
fINPUT = CLKIN 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table 16. All of the timing specifications for the ADSP-21469
peripherals are defined in relation to tPCLK. See the peripheral
specific section for each peripheral’s timing information.
Figure 5 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.
Table 16. Clock Periods
Timing
Requirements
Description
tCK
CLKIN Clock Period
tCCLK
Processor Core Clock Period
tPCLK
Peripheral Clock Period = 2 × tCCLK
相關(guān)PDF資料
PDF描述
DS1620S+ IC THERMOMETER/STAT DIG 8-SOIC
XC2C384-10FGG324I IC CR-II CPLD 384MCELL 324-FBGA
MAX31855JASA+ IC CONV THERMOCOUPLE-DGTL 8SOIC
VE-B1N-CW-B1 CONVERTER MOD DC/DC 18.5V 100W
ADSP-21489BSWZ-4B IC CCD SIGNAL PROCESSOR 176LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21469KBCZ-4 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP21469KBCZENG 制造商:Analog Devices 功能描述:
ADSP-21469KBCZ-ENG 制造商:Analog Devices 功能描述:FXD PT PROC - Trays
ADSP-21469KBCZ-X 制造商:Analog Devices 功能描述:FXD PT PROC - Trays
ADSP-21469KBZ-EN 制造商:Analog Devices 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*