參數(shù)資料
型號： ADSP-21369BSWZ-2A
廠商： Analog Devices Inc
文件頁數(shù)： 5/64頁
文件大小： 0K
描述： IC DSP 32BIT 333MHZ 208-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點
接口： DAI，DPI
時鐘速率： 333MHz
非易失內(nèi)存： ROM（768 kB）
芯片上RAM： 256kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤
Rev. F
|
Page 13 of 64
|
October 2013
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 8:
A = asynchronous, G = ground, I = input, O = output,
O/T = output three-state, P = power supply, S = synchronous,
(A/D) = active drive, (O/D) = open-drain, (pd) = pull-down
resistor, (pu) = pull-up resistor.
The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-
sors use extensive pin multiplexing to achieve a lower pin count.
For complete information on the multiplexing scheme, see the
ADSP-21368 SHARC Processor Hardware Reference, “System
Design” chapter.
Table 8. Pin Descriptions
Name
Type
State During/
After Reset
(ID = 00x)
Description
ADDR23–0
O/T (pu)1
Pulled high/
driven low
External Address. The processors output addresses for external memory and peripher-
als on these pins.
DATA31–0
I/O (pu)1
Pulled high/
pulled high
External Data. Data pins can be multiplexed to support external memory interface data
(I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode
and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_P-
DAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input data.
ACK
I (pu)
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other periph-
erals to hold off completion of an external memory access.
MS0–1
O/T (pu)1
Pulled high/
driven high
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS3-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory access
is occurring, the MS3-0 lines are inactive; they are active, however, when a conditional
memory access instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. See the processor hardware
reference for more information.
RD
O/T (pu)1
Pulled high/
driven high
External Port Read Enable. RD is asserted whenever the processors read a word from
external memory.
WR
O/T (pu)1
Pulled high/
driven high
External Port Write Enable. WR is asserted when the processors write a word to external
memory.
FLAG[0]/IRQ0
I/O
FLAG[0] INPUT
FLAG0/Interrupt Request 0.
FLAG[1]/IRQ1
I/O
FLAG[1] INPUT
FLAG1/Interrupt Request 1.
FLAG[2]/IRQ2/
MS2
I/O with pro-
grammablepu
(for MS mode)
FLAG[2] INPUT
FLAG2/Interrupt Request 2/Memory Select 2.
FLAG[3]/
TMREXP/MS3
I/O with pro-
grammablepu
(for MS mode)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select 3.
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