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參數(shù)資料
| 型號： | ADSP-21366SKBCZENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | LEAD FREE, MO-205AE, MBGA-136 |
| 文件頁數(shù)： | 8/54頁 |
| 文件大小： | 559K |
| 代理商： | ADSP-21366SKBCZENG |
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Rev. PrA
|
Page 8 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
Timers
The ADSP-21365/6 has a total of four timers: a core timer that
can generate periodic software interrupts and three general pur-
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
Pulse Waveform Generation mode
Pulse Width Count /Capture mode
External Event Watchdog mode
The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general purpose timers independently.
ROM Based Security
The ADSP-21365/6 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation fea-
tures and external boot modes are only available after the
correct key is scanned.
Program Booting
The internal memory of the ADSP-21365/6 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins (see
Table 6 on
page 14
). Selection of the boot source is controlled via the SPI as
either a master or slave device, or it can immediately begin exe-
cuting from ROM.
Phase-Locked Loop
The ADSP-21365/6 uses an on-chip Phase-Locked Loop (PLL)
to generate the internal clock for the core. On power up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1
(see
Table 7 on page 14
). After booting, numerous other ratios
can be selected via software control.
The ratios are made up of software configurable numerator val-
ues from 1 to 64 and software configurable divisor values of 1, 2,
4, and 8.
Power Supplies
The ADSP-21365/6 has separate power supply connections for
the internal (V
DDINT
), external (V
DDEXT
), and analog
(A
VDD
/A
VSS
) power supplies. The internal and analog supplies
must meet the 1.2V requirement. The external supply must
meet the 3.3V requirement. All external supply pins must be
connected to the same power supply.
Note that the analog supply (A
VDD
) powers the ADSP-21365/6’s
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the A
VDD
pin. Place the filter as close as possible to the pin. For
an example circuit, see
Figure 4
. To prevent noise coupling, use
a wide trace for the analog ground (A
VSS
) signal and install a
decoupling capacitor as close as possible to the pin. Note that
the A
and A
VDD
pins specified in
Figure 4
are inputs to the
processor and not the analog ground plane on the board.
For
more information, see Electrical Characteristics on page 15.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21365/6
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor's JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-21365/6 is supported with a complete set of
CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21365/6.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
Figure 4. Analog Power (A
VDD
) Filter Circuit
V
DDINT
A
VDD
A
VSS
0.01 F
0.1 F
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADSP-21366SKSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366WBBCZ-1A | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366YSWZ-2AA | 功能描述:IC DSP 32BIT 200MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21367 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processors |
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