參數(shù)資料
型號(hào): ADSP-21364SCSQ-ENG
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝: MS-026BFB-HD, HSLQFP-144
文件頁(yè)數(shù): 34/52頁(yè)
文件大?。?/td> 853K
代理商: ADSP-21364SCSQ-ENG
Rev. PrB
|
Page 34 of 52
|
September 2004
ADSP-21364
Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in
Table 30
are valid at the DAI_P20–1 pins.
Table 30. SRC, Serial Input Port
Parameter
Timing Requirements
t
SIFS
1
t
SIHFS
1
t
SISD
1
t
SIHD
1
t
IDPCLKW
t
IDPCLK
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
Min
Max
Unit
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
4
5.5
4
5.5
9
20
ns
ns
ns
ns
ns
ns
Figure 25. SRC Serial Input Port Timing
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
SAMPLE EDGE
t
SISD
t
SIHD
t
SISFS
t
SIHFS
t
IDPCLKW
DAI_P20-1
(SDATA)
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