參數(shù)資料
型號(hào)： ADSP-21364SCSQ-ENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： MS-026BFB-HD, HSLQFP-144
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 853K
代理商： ADSP-21364SCSQ-ENG
Rev. PrB
|
Page 30 of 52
|
September 2004
ADSP-21364
Preliminary Technical Data
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
t
DDTEN
1
t
DDTTE
1
t
DDTIN
1
1
Referenced to drive edge.
Min
Max
Unit
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
2
ns
ns
ns
7
–1
Table 27. Serial Ports—External Late Frame Sync
Parameter
Switching Characteristics
t
DDTLFSE
1
Min
Max
Unit
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
1
7
ns
ns
t
DDTENFS
1
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
0.5
Figure 21. External Late Frame Sync
1
1
This figure reflects changes made to support Left-justified Sample Pair mode.
DRIVE
SAMPLE
DRIVE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE
SAMPLE
DRIVE
LATE EXTERNAL TRANSMIT FS
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
1ST BIT
2ND BIT
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
1ST BIT
2ND BIT
t
HFSE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
NOTE
SERIAL PORT SIGNALS (SCLK, FS,
DATA CHANNEL A/B
) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
t
HFSE/I
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相關(guān)代理商/技術(shù)參數(shù)
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ADSP-21364SCSQZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
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ADSP-21364SKSQZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
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