參數(shù)資料
型號： ADSP-21267SKBCZ-X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Preliminary Technical Data
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁數(shù)： 28/44頁
文件大?。?/td> 454K
代理商： ADSP-21267SKBCZ-X
Rev. PrA
|
Page 28 of 44
|
January 2004
ADSP-21267
PRELIMINARY TECHNICAL DATA
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P[20:1] pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P[20:1] pins.
Table 22. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
Receive Data Setup Before Receive SCLK
1
Receive Data Hold After SCLK
1
SCLK Width
SCLK Period
2.5
ns
t
HFSE
2.5
2.5
2.5
7
20
ns
ns
ns
ns
ns
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
Switching Characteristics
t
DFSE
FS Delay After SCLK
(Internally Generated FS in Ether Transmit or Receive Mode)
2
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode
2
)
Transmit Data Delay After Transmit SCLK
2
Transmit Data Hold After Transmit SCLK
2
7
ns
t
HOFSE
2
ns
ns
ns
t
DDTE
t
HDTE
7
2
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 23. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
Receive Data Setup Before SCLK
1
Receive Data Hold After SCLK
1
6
ns
t
HFSI
1.5
6
1.5
ns
ns
ns
t
SDRI
t
HDRI
Switching Characteristics
t
DFSI
t
HOFSI
t
DFSI
t
HOFSI
t
DDTI
t
HDTI
t
SCLKIW
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
2
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
2
Transmit Data Delay After SCLK
2
Transmit Data Hold After SCLK
2
Transmit or Receive SCLK Width
3
ns
ns
ns
ns
ns
ns
ns
-1.0
3
-1.0
3
-1.0
0.5t
SCLK
– 2
0.5t
SCLK
+ 2
1
Referenced to the sample edge.
2
Referenced to drive edge.
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相關(guān)代理商/技術(shù)參數(shù)
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