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參數(shù)資料
| 型號： | ADSP-21267SKBCZ-X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Preliminary Technical Data |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 15/44頁 |
| 文件大小： | 454K |
| 代理商： | ADSP-21267SKBCZ-X |
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ADSP-21267
Rev. PrA
|
Page 15 of 44
|
January 2004
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
TIMING SPECIFICATIONS
The ADSP-21267’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP’s internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The ADSP-21267’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (
Table 7
).
Internal (Core) Supply Voltage (V
DDINT
)
1
Analog (PLL) Supply Voltage (A
VDD
)
1
External (I/O) Supply Voltage (V
DDEXT
)
1
Input Voltage
Output Voltage Swing
Load Capacitance
1
Storage Temperature Range
1
Junction Temperature under Bias
-0.3 V to +1.4 V
-0.3 V to +1.4 V
-0.3 V to +3.8 V
-0.5 V to V
DDEXT1
+ 0.5 V
-0.5 V to V
DDEXT1
+ 0.5 V
200 pF
-65
°
C to +150
°
C
125
°
C
1
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21267 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
Table 7. ADSP-21267 CLKOUT and CCLK Clock Generation Operation
Timing Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/t
CK
1/t
CCLK
Timing Requirements
t
CK
t
CCLK
t
SCLK
t
SPICLK
Description
1
CLKIN Clock Period
(Processor) Core Clock Period
Serial Port Clock Period = (t
CCLK
) x SR
SPI Clock Period = (t
CCLK
) x SPIR
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
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| ADSP-21267SKSTZ-X | Preliminary Technical Data |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADSP-21267SKSTZ-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21362 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| adsp-21362bbc-1aa | 制造商:Analog Devices 功能描述: |
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| ADSP-21362BSWZ-1AA | 功能描述:IC DSP 32BIT 333MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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