參數(shù)資料
型號(hào)： ADSP-21262SBBCZ150
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Embedded Processor
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁(yè)數(shù)： 8/48頁(yè)
文件大?。?/td> 401K
代理商： ADSP-21262SBBCZ150
Rev. B
|
Page 8 of 48
|
August 2005
ADSP-21262
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21262 SPI-compatible peripheral
implementation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21262 SPI-
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz is equivalent to
66M byte/sec, and a clock rate of 150 MHz is equivalent to
50M byte/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.
Timers
The ADSP-21262 has a total of four timers: a core timer able to
generate periodic software interrupts, and three general-pur-
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
Pulse waveform generation mode
Pulse width count/capture mode
External event watchdog mode
The core timer can be configured to use FLAG3 as a timer
expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general-purpose timers independently.
Program Booting
The internal memory of the ADSP-21262 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the boot configuration (BOOTCFG1–0) pins. Selection of the
boot source is controlled via the SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Phase-Locked Loop
The ADSP-21262 uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power-up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21262 has separate power supply connections for the
internal (V
DDINT
), external (V
DDEXT
), and analog (A
VDD
/A
VSS
)
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply pin (A
VDD
) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
A
VDD
pin. Place the filter components as close as possible to the
A
VDD
/A
VSS
pins. For an example circuit, see
Figure 4
. (A recom-
mended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
DDINT
and GND. Use wide traces
to connect the bypass capacitors to the analog power (A
VDD
) and
ground (A
VSS
) pins. Note that the A
VDD
and A
VSS
pins specified
in
Figure 4
are inputs to the processor and not the analog
ground plane on the board—the A
VSS
pin should connect
directly to digital ground (GND) at the chip.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21262 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
Figure 4. Analog Power Filter Circuit
HI Z FERRITE
BEAD CHIP
LOCATE ALL COMPONENTS
CLOSE TO AVDDAND AVSSPINS
AVDD
AVSS
100nF
10nF
1nF
ADSP-21262
VDDINT
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ADSP-21262SKBC200R 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA T/R
ADSP-21262SKBC-200X 制造商:Analog Devices 功能描述:
ADSP-21262SKBCZ200 功能描述:IC DSP CTLR 32BIT 136CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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