參數(shù)資料
型號(hào)： ADSP-21061KSZ-160
廠商： Analog Devices Inc
文件頁數(shù)： 9/52頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 1MBIT 240MQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 240-MQFP-EP（32x32）
包裝： 托盤
Rev. D | Page 17 of 52 | May 2013
ADSP-21061L SPECIFICATIONS
OPERATING CONDITIONS (3.3 V)
ELECTRICAL CHARACTERISTICS (3.3 V)
A Grade
K Grade
Parameter
Description
Min
Nom
Max
Min
Nom
Max
Unit
VDD
Supply Voltage
3.15
3.3
3.45
3.15
3.3
3.45
V
TCASE
Case Operating Temperature
–40
+85
0
+85
C
VIH11
1 Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0,
TFS1, RFS0, RFS1, EBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1
High Level Input Voltage @ VDD = Max
2.0
VDD + 0.5
2.0
VDD + 0.5
V
VIH22
2 Applies to input pins: CLKIN, RESET, TRST
High Level Input Voltage @ VDD = Max
2.2
VDD + 0.5
2.2
VDD + 0.5
V
VIL 1, 2
Low Level Input Voltage @ VDD = Min
–0.5
+0.8
–0.5
+0.8
V
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1,2
High Level Output Voltage
@ VDD = Min, IOH = –2.0 mA
2.4
V
Low Level Output Voltage
@ VDD = Min, IOL = 4.0 mA
0.4
V
IIH3, 4
High Level Input Current
@ VDD = Max, VIN = VDD Max
10
μA
IIL3
Low Level Input Current
@ VDD = Max, VIN = 0 V
10
μA
IILP4
Low Level Input Current
@ VDD = Max, VIN = 0 V
150
μA
IOZH5, 6, 7, 8
Three-State Leakage Current
@ VDD = Max, VIN = VDD Max
10
μA
IOZL5
Three-State Leakage Current
@ VDD = Max, VIN = 0 V
10
μA
IOZHP
Three-State Leakage Current
@ VDD = Max, VIN = VDD Max
350
μA
IOZLC7
Three-State Leakage Current
@ VDD = Max, VIN = 0 V
1.5
mA
IOZLA9
Three-State Leakage Current
@ VDD = Max, VIN = 1.5 V
350
μA
IOZLAR8
Three-State Leakage Current
@ VDD = Max, VIN = 0 V
4.2
mA
IOZLS6
Three-State Leakage Current
@ VDD = Max, VIN = 0 V
150
μA
CIN10, 11
Input Capacitance
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
4.7
pF
1 Applies to output and bidirectional pins: DATA47–0, ADDR31–0, 3-0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.
2 See “Output Drive Currents” on Page 45 for typical drive current capabilities.
3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4 Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI, EMU.
5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,
TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-21061 is not requesting bus
mastership.)
6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7 Applies to CPA pin.
8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-21061L
is not requesting bus mastership).
9 Applies to ACK pin when keeper latch enabled.
10Applies to all signal pins.
11Guaranteed but not tested.
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