參數資料
型號: ADS931
英文描述: 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 8位,30MHz的采樣模擬數字轉換器
文件頁數: 2/12頁
文件大?。?/td> 210K
代理商: ADS931
2
ADS931
SPECIFICATIONS
At T
= full specified temperature range unless otherwise noted. +V
= LV
= +3V, specified single-ended input (1V to 2V) and sampling rate = 30MHz, unless
otherwise specified. The input range is 2.25V to 3.25V when specified for +5V operation.
ADS931E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
8
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
–40 to +85
°
C
ANALOG INPUT
Specified Full Scale Input Range
(1)
Common-mode Voltage
Analog Input Bias Current
Input Impedance
1Vp-p
+1.0
+2.0
V
V
μ
A
+1.5
1
1.25 || 5
M
|| pF
DIGITAL INPUTS
Logic Family
High Input Voltage, V
IH
Low Input Voltage, V
IL
High Input Current, I
IH
Low Input Current, I
IL
Input Capacitance
TTL/HCT Compatible CMOS
+2.0
LV
DD
+0.8
V
V
μ
A
μ
A
pF
±
10
±
10
5
CONVERSION CHARACTERISTICS
Start Conversion
Sample Rate
Data Latency
Rising Edge of Convert Clock
10k
30M
Samples/s
Clk Cycles
5
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500MHz
f = 12.5MHz
No Missing Codes
Integral Nonlinearity Error, f = 500kHz
Spurious Free Dynamic Range
(2)
f = 500kHz (–1dBFS input)
f = 12.5MHz (–1dBFS input)
Two-Tone Intermodulation Distortion
(4)
f = 3.6MHz and 3.5MHz
(–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12.5MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 12.5MHz (–1dBFS input)
Effective Number of Bits
Differential Gain Error
Differential Phase Error
Output Noise
Aperture Delay Time
Aperture Jitter
Analog Input Bandwidth
Small Signal
Full Power
Overvoltage Recovery Time
(6)
V
S
= +3V and +5V
±
0.7
±
0.7
±
1.0
LSB
LSB
V
S
= +3V and +5V
V
S
= +3V and +5V
V
S
= +3V and +5V
Guaranteed
±
1.0
±
2.5
LSB
49
49
dBFS
(3)
dBFS
43
54
dBFS
V
S
= +3V and +5V
48
48
dB
dB
44
V
S
= +3V and +5V
45
45
7.2
2.3
1
0.2
2
7
dB
dB
Bits
%
40
f = 12MHz
(5)
NTSC, PAL
NTSC, PAL
Input AC-Grounded
degrees
LSBs rms
ns
ps rms
–20dBFS Input
0dBFS Input
350
100
2
MHz
MHz
ns
DIGITAL OUTPUTS
Logic Family
Logic Coding
High Output Voltage, V
OH
Low Output Voltage, V
OL
3-State Enable Time
3-State Disable Time
Internal Pull-Down
Power-Down Enable Time
Power-Down Disable Time
Internal Pull-Down
C
L
= 15pF
TTL/HCT Compatible CMOS
Straight Offset Binary
2.4
V
DD
0.4
40
10
V
V
ns
ns
k
ns
ns
k
OE = L
OE = H
20
2
50
133
18
50
Pwrdn = L
Pwrdn = H
ACCURACY
Gain Error
Input Offset
(7)
Power Supply Rejection (Gain)
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
V
S
= +3V and +5V
2.4
±
6.5
75
2
1
3.5
±
25
%FS
mV
dB
V
V
k
Referred to Ideal Midscale
V
S
= +10%
42
REFB +0.5
0.8
V
–0.8
REFT –0.5
4
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