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參數(shù)資料
| 型號： | ADS931 |
| 英文描述： | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 8位，30MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 210K |
| 代理商： | ADS931 |
12
ADS931
duty cycle, along with fast rise and fall times (2ns or less),
are recommended to meet the rated performance specifica-
tions. However, the ADS931 performance is tolerant to duty
cycle variations of as much as
±
10%, which should not
affect the performance. For applications operating with
input frequencies up to Nyquist (f
CLK
/2) or undersampling
applications, special consideration must be made to provide
a clock with very low jitter. Clock jitter leads to aperture
jitter (t
A
) which can be the ultimate limitation to achieving
good SNR performance. Equation (5) shows the relationship
between aperture jitter, input frequency and the signal-to-
noise ratio:
SNR = 20log10 [1/(2
π
f
IN
t
A
)]
(5)
DIGITAL OUTPUTS
The digital outputs of the ADS931 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V
OL
= 0.4V, V
OH
= 2.4V, which allows
the ADS931 to directly interface to 3V logic. The digital
output driver of the ADS931 uses a dedicated digital supply
pin (pin 2, LV
DD
), see Figure 8. By adjusting the voltage on
LV
DD
, the digital output levels will vary respectively. It is
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the A/D converter
from any digital activities on the bus coupling back high
frequency noise, which degrades the performance.
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS931 has several supply pins, one of which is
dedicated to supply only the output driver (LV
DD
). The
remaining supply pins are not divided into analog and digital
supply pins (+V
S
) since they are internally connected on the
chip. For this reason, it is recommended that the converter be
treated as an analog component and to power it only from
the analog supply. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 9 shows the recommended decoupling scheme for the
analog supplies. In most cases, 0.1
μ
F ceramic chip capaci-
tors are adequate to keep the impedance low over a wide
frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins. In
addition, one larger bipolar capacitor (1
μ
F to 22
μ
F) should
be placed on the PC board in proximity of the converter
circuit.
+V
S
+LV
DD
ADS931
Digital
Output
Stage
FIGURE 8. Independent Supply Connection for Output
Stage.
TABLE I. Coding Table for the ADS931.
+FS (IN = REFT Voltage)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = REFB Voltage)
11111111
11111111
11111110
11100000
11000000
10100000
10000001
10000000
01111111
01100000
01000000
00100000
00000001
00000000
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
SINGLE-ENDED INPUT
POWER-DOWN MODE
The ADS931’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down pin (pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 84%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50k
).
FIGURE 9. Recommended Bypassing for Analog Supply
Pins.
+V
S
1
13
14
GND
ADS931
0.1μF
+V
S
18
19
20
GND
0.1μF
+V
S
28
0.1μF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS-931 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit 1MHZ Sampling A/D Converters |
| ADS931E | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS931E | 制造商:Texas Instruments 功能描述:IC 8BIT ADC 30MSPS 28SSOP 制造商:Texas Instruments 功能描述:IC, 8BIT ADC, 30MSPS, 28SSOP 制造商:Texas Instruments 功能描述:IC, 8BIT ADC, 30MSPS, 28SSOP; Resolution (Bits):8bit; Sampling Rate:33MSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Supply Current:23mA; Digital IC Case Style:SSOP; No. of Pins:28; Input Channel ;RoHS Compliant: Yes |
| ADS931E/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS931E/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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