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參數(shù)資料
| 型號： | ADS902E |
| 英文描述： | 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，30MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 194K |
| 代理商： | ADS902E |
10
ADS902
When selecting this reference circuit, the trade-offs are
variations in the reference voltages due to component toler-
ances and power supply variations. In either case, it is
recommended to bypass the reference ladder with at least
0.1
μ
F ceramic capacitors as shown in Figure 6. The purpose
of the capacitors is twofold; they will bypass most of the
high frequency transient noise which results from feedthrough
of the clock and switching noise from the S/H stages and
secondly, they serve as a charge reservoir to supply instan-
taneous current to internal nodes.
PRECISE REFERENCE SOLUTION
For those applications requiring a higher level of dc accu-
racy and drift, a reference circuit with a precision reference
element might be used (see Figure 7). A stable +2.5V
reference voltage is established by a two terminal bandgap
reference diode, the REF1004-2.5. Using a general-purpose
single-supply dual operational amplifier (A1), like an
OPA2237, OPA2234 or MC34072, the two required refer-
ence voltages for the ADS902 can be generated by setting
each op amp to the appropriate gain. For example, set REFT
to +3.25V and REFB to +2.25V.
consideration must be made to provide a clock with very low
jitter. Clock jitter leads to aperture jitter (t
A
) which can be the
ultimate limitation to achieving good SNR performance.
Equation (5) shows the relationship between aperture jitter,
input frequency and the signal-to-noise ratio:
SNR = 20log
10
[1/(2
π
f
IN
t
A
)]
(5)
For example, with a 5MHz full-scale input signal and an
aperture jitter of t
A
= 20ps rms, the SNR is clock jitter
limited to 54dB.
DIGITAL OUTPUTS
The digital outputs of the ADS902 are standard CMOS
stages and designed to be compatible with both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V
OL
= 0.4V, V
OH
= 2.4V, which allows
the ADS902 to directly interface to 3V-logic. The digital
outputs of the ADS902 uses a dedicated digital supply pin
(see Figure 8). By adjusting the voltage on LV
DD
, the digital
output levels will vary respectively. In any case, it is recom-
mended to limit the fan-out to one, in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
which provide the added benefit of isolating the A/D con-
verter from any digital activities on the bus from coupling
back high frequency noise and degrading the performance.
The standard output coding is Straight Offset Binary where
the full scale input signal corresponds to all “1”s at the
output (see Table I). The digital outputs of the ADS902 can
be set to a high impedance state by driving the OE (pin 16)
with a logic “H”. Normal operation is achieved with a “L”
at OE or left unconnected due to the internal pull-down
resistor.
+FS (IN = +3.25V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +2.75V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +2.25V)
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
SINGLE-ENDED INPUT
TABLE I. Coding Table for the ADS902.
1/2 A
1
R
F1
R
G1
3k
5k
REF1004
+2.5V
10k
10
Top
Reference
(Pin 22)
+V
S
+V
S
1/2 A
1
R
F2
R
G2
10
Bottom
Reference
(Pin 24)
A
1
= OPA2237 or Equivalent.
FIGURE 7. Precise Solution to Supply External Reference
Voltages to the ADS902.
FIGURE 8. Independent Supply Connection for Output
Stage.
+V
S
1,18, 28
2
+LV
DD
ADS902
Digital
Output
Stage
CLOCK INPUT
The clock input of the ADS902 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support maximum sampling rates (30MSPS), high speed or
advanced CMOS logic should be used (HC/HCT, AC/ACT).
When digitizing at high sampling rates, a 50% duty cycle
along with fast rise and fall times (2ns or less) are recom-
mended to meet the rated performance specifications. How-
ever, the ADS902 performance is tolerant of duty-cycle
variations of as much as
±
5%, which should not affect
performance. For applications operating with input frequen-
cies up to Nyquist or undersampling applications, special
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS902E/1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| ADS9110EVM-PDK | 功能描述:ADS9110 - 18 Bit 2M Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:texas instruments 系列:- 零件狀態(tài):有效 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):18 采樣率（每秒）:2M 數(shù)據(jù)接口:串行 輸入范圍:±VREF 不同條件下的功率（典型值）:15mW @ 2MSPS 使用的 IC/零件:ADS9110 所含物品:2 板，線纜 標(biāo)準(zhǔn)包裝:1 |
| ADS9110IRGER | 功能描述:18 Bit Analog to Digital Converter 1 Input 1 SAR 24-VQFN (4x4) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):18 采樣率（每秒）:2M 輸入數(shù):1 輸入類型:差分 數(shù)據(jù)接口:SPI 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):SAR 參考類型:外部 電壓 - 電源，模擬:1.65 V ~ 1.95 V 電壓 - 電源，數(shù)字:1.65 V ~ 1.95 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-VQFN（4x4） 標(biāo)準(zhǔn)包裝:1 |
| ADS9110IRGET | 功能描述:ANALOG TO DIGITAL CONVERTERS - A 制造商:texas instruments 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-VQFN（4x4） 標(biāo)準(zhǔn)包裝:250 |
| ADS9120EVM-PDK | 功能描述:EVAL BOARD FOR ADS9120 制造商:texas instruments 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):16 采樣率（每秒）:2.5M 數(shù)據(jù)接口:SPI 輸入范圍:±VREF 不同條件下的功率（典型值）:9mW @ 2.5MSPS 使用的 IC/零件:ADS9120 所含物品:板，電纜 標(biāo)準(zhǔn)包裝:1 |
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