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參數(shù)資料
| 型號： | ADS902 |
| 英文描述： | 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，30MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 194K |
| 代理商： | ADS902 |
2
ADS902
SPECIFICATIONS
At T
A
= +25
°
C, V
S
= LV
DD
= +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.
ADS902E
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution
Specified Temperature Range
10
10
Bits
°
C
Ambient Air
–40
+85
–40
+85
ANALOG INPUT
Specified Full Scale Input Range
(1)
Common-Mode Voltage (Midscale)
Track-Mode Input Bandwidth
Analog Input Bias Current
Input Impedance
1
2
3
6
6
6
Vp-p
V
MHz
μ
A
M
|| pF
+2.75
350
1
1.25 || 5
DIGITAL INPUTS
Logic Family
High Input Voltage, V
IH
Low Input Voltage, V
IL
High Input Current, I
IH
Low Input Current, I
IL
Input Capacitance
+2.0
+V
S
+0.8
6
6
6
V
V
μ
A
μ
A
pF
±
10
±
10
5
6
6
6
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
Full
10k
30M
6
6
Samples/s
Clk Cyc
5
6
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 500kHz
f = 12.5MHz
No Missing Codes
Spurious-Free Dynamic Range
f = 12.5MHz (–1dBFS
(2)
input)
Integral Nonlinearity Error, f = 500kHz
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12.5MHz (–1dBFS input)
Maximum SNR
f = 9MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 3.58MHz (–1dBFS input)
f = 12.5MHz (–1dBFS) input)
Effective Number of Bits
(3)
, f =12.5MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Full
Full
Full
±
0.3
±
0.3
±
1.0
±
1.0
6
6
6
6
LSB
LSB
Guaranteed
Guaranteed
Full
Full
53
±
2.0
50
58
6
dB
LSB
±
4.5
6
Referred to Sinewave Input Signal
Full
Full
48
48
53
53
dB
dB
52
57
Referred to DC FS Input Signal
62
66
dB
Full
Full
Full
46
45
45
50
50
49
7.8
0.2
4
7
dB
dB
dB
Bits
47
53
Input Grounded
6
6
6
LSB rms
ns
ps rms
DIGITAL OUTPUTS
Logic Family
Logic Coding
High Output Voltage, V
OH
Low Output Voltage, V
OL
3-State Enable Time
3-State Disable Time
OE Internal Pull-Down to Gnd
Power-Down Enable Time
Power-Down Disable Time
Power-Down Internal Pull-Down to Gnd
C
L
= 15pF
+2.4
LV
DD
+0.4
40
10
6
6
6
6
6
V
V
ns
ns
k
ns
ns
k
OE = L
OE = H
20
18
50
133
18
50
6
6
6
6
6
6
Pwrdn = L
Pwrdn = H
ACCURACY
Gain Error
Input Offset Error
(4)
Power Supply Rejection (Gain)
Power Supply Rejection (Offset)
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
Full
Full
Full
Full
Full
Full
0.5
1.4
56
68
+3.25
+2.25
4
1
6
6
6
+4
+2
6
%FS
%FS
dB
dB
V
V
k
V
S
=
±
5%
V
S
=
±
5%
42
42
6
6
6
6
REFB +0.5
+0.8
V
–0.8
REFT –0.5
6
6
REFT to REFB
1Vp-p
2Vp-p
TTL/HCT Compatible CMOS
TTL/HCT Compatible CMOS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
TTL/HCT Compatible CMOS
Straight Offset Binary
TTL/HCT Compatible CMOS
Straight Offset Binary
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