參數(shù)資料
型號: ADS8509
英文描述: 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
中文描述: 16位250 ksps的串行CMOS采樣模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 16/26頁
文件大?。?/td> 693K
代理商: ADS8509
www.ti.com
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8192 Points,
f
s
= 250 KSPS,
f
= 20 kHz, 0 dB
SINAD = 86.0 dB,
THD = 98.7 dB
A
f Frequency kHz
Figure 26.
BASIC OPERATION
Two signals control conversion in the ADS8509: CS and R/C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
READING DATA
The conversion result is available as soon as BUSY returns to high therefore, data always represents the
conversion previously completed even when it is read during a conversion. The ADS8509 outputs serial data in
either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up will not produce a valid conversion result.
INTERNAL DATACLK
In the internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
ADS8509
SLAS324A–OCTOBER 2004–REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
FFT (20 kHz Input)
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8509 will clock out data whenever
R/C is brought high and the external clock is active. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/C. The ADS8509 provides a TAG input for cascading multiple
converters together.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin
controls this function. If external clock is used the TAG input can be used to daisy-chain multiple ADS8509 data
pins together.
The DATACLK pin becomes an output when EXT/INT is low. 16 clock pulses are generated at the beginning of
each conversion after timing t
8
is satisfied, i.e. you can only read previous conversion result during conversion.
DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. DATA pin returns to the state of TAG pin
input sensed at the start of transmission.
16
相關(guān)PDF資料
PDF描述
ADS8509IBDB 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
ADS8509IBDBR 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
ADS8509IDWRG4 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
ADS8509IBDW 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
ADS8509IBDWR 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
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