參數(shù)資料
型號： ADS8506IDW
英文描述： 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
中文描述： 12位40 kSPS的低功耗采樣模擬到數(shù)字轉(zhuǎn)換的內(nèi)部基準，并行/串行接口
文件頁數(shù)： 5/28頁
文件大?。?/td> 426K
代理商： ADS8506IDW
www.ti.com
ADS8506
SLAS484A–SEPTEMBER 2007–REVISED OCTOBER 2007
Terminal Functions
TERMINAL
NO.
1
2
3
4
5
DIGITAL
I/O
DESCRIPTION
NAME
R1
IN
AGND1
R2
IN
CAP
REF
Analog Input.
Analog sense ground. Used internally as ground reference point. Minimal current flow
Analog Input.
Reference buffer output. 2.2-
μ
F Tantalum capacitor to ground.
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-
μ
F tantalum capacitor.
Analog ground
Selects straight binary or binary 2's complement for output data format. if high, data is output in a
straight binary format. If low, data is output in a binary 2's complement format.
Selects external/Internal data clock for transmitting data. If high, data is output synchronized to
the clock input on DATACLK. If low, a convert command initiates the transmission of the data
from the previous conversion, along with 12-clock pulses output on DATACLK.
Data bit 3 if BYTE is high. Data bit 11 (MSB) if BYTE is low. Hi-Z when CS is high and/or R/C is
low. Leave unconnected when using serial output.
Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. Hi-Z when CS is high and/or R/C is
low.
Ground if BYTE is high. Data bit 7 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
Digital ground
Ground if BYTE is high. Data bit 6 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
Ground if BYTE is high. Data bit 5 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
Ground if BYTE is high. Data bit 4 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
Either an input or an output depending on the EXT/INT level. Output data is synchronized to this
clock. If EXT/INT is low, DATACLK transmits 12 pulses after each conversion, and then remains
low between conversions.
Serial data output. Data is synchronized to DATACLK, with the format determined by the level of
SB/BTC. In the external clock mode, after 12 bits of data, the ADC outputs the level input on
TAG as long as CS is low and R/C is high. If EXT/INT is low, data is valid on both the rising and
falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG input
when the conversion was started.
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that is dependent on the external clock mode.
Selects 8 most significant bits (low) or 8 least significant bits (high) on parallel output pins.
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of
the data results from the previous conversion.
Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new conversion. If
EXT/INT is low, this same falling edge will start the transmission of serial data results from the
previous conversion.
At the start of a conversion, BUSY goes low and stays low until the conversion is completed and
the digital outputs have been updated.
Power down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
REFD High shuts down the internal reference. External reference will be required for
conversions.
Analog Supply. Nominally +5 V. Decouple with 0.1-
μ
F ceramic and 10-
μ
F tantalum capacitors.
Digital Supply. Nominally +5 V. Connect directly to pin 27. Must be
≤
V
ANA
.
6
7
AGND2
SB/BTC
I
8
EXT/INT
I
9
D7
O
10
11
12
D6
D5
D4
O
O
O
13
14
15
16
17
18
D3
DGND
D2
D1
D0
DATACLK
O
O
O
O
I/O
19
SDATA
O
20
TAG
I
21
22
BYTE
R/C
I
I
23
CS
I
24
BUSY
O
25
PWRD
I
26
REFD
I
27
28
V
ANA
V
DIG
Copyright 2007, Texas Instruments Incorporated
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參數(shù)描述
ADS8506IDWG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8506IDWR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8506IDWRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507 制造商:BB 制造商全稱:BB 功能描述:16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507I 制造商:BB 制造商全稱:BB 功能描述:16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
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