- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362147 > ADS8506IDW 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE PDF資料下載
參數(shù)資料
| 型號： | ADS8506IDW |
| 英文描述： | 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE |
| 中文描述： | 12位40 kSPS的低功耗采樣模擬到數(shù)字轉(zhuǎn)換的內(nèi)部基準(zhǔn)，并行/串行接口 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 426K |
| 代理商： | ADS8506IDW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
www.ti.com
External
DATACLK
.
2
3
4
27
26
28
13
12
16
17
15
1
Null
D
Q
A00
D
Q
Null
D
Q
B00
D
Q
A11
D
Q
A12
D
Q
B11
D
Q
B12
D
Q
TAG(A)
TAG(B)
SDATA(A)
SDATA (B)
DATACLK
(both A & B)
SYNC
(both A & B)
(both A & B)
SDATA ( B )
Nth Conversion Data
Null
B
B11
A11
B00
B9
B10
B01
A00
A10
A9
A01
SDATA ( A )
A11
A00
A9
A10
A01
14
Null
A
Null
A
ADS8506A
TAG
DCS
R/C
DATACLK
ADS8506B
TAG
DATA
CS
R/C
DATACLK
Processor
SCLK
SDI
TAG(A) = 0
TAG(A) = 0
R/C
BUSY
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
INPUT RANGES
ADS8506
SLAS484A–SEPTEMBER 2007–REVISED OCTOBER 2007
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the t
d11
constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in
Figure 40
, that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 12 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in
Figure 40
the NULL bit becomes a zero between each data
word.
Figure 40. Timing of TAG Feature With Single Conversion (Using External DATACLK)
The ADS8506 offers three input ranges: standard ±10-V and 0-V to 5-V ranges, and a 0-V to 4-V range for
complete, single-supply systems. See
Figure 42
and
Figure 43
for the necessary circuit connections for
implementing each input range and optional offset and gain adjust circuitry. Offset and full-scale error
specifications are tested with the fixed resistors, see
Figure 43
(full-scale error includes offset and gain errors
measured at both +FS and -FS). Adjustments for offset and gain are described in the Calibration section of this
data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
The input impedance, summarized in
Table 1
, results from the combination of the internal resistor network (see
the front page of this product data sheet) and the external resistors used for each input range (see
Figure 44
).
The input resistor divider network provides inherent over-voltage protection to at least ±5.5 V for R2
IN
and ±12 V
for R1
IN
.
Analog inputs above or below the expected range yields either positive full-scale or negative full-scale digital
outputs, respectively. Wrapping or folding over for analog inputs outside the nominal range does not occur.
20
Submit Documentation Feedback
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s):
ADS8506
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS8506IDWR | 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE |
| ADS976 | Converter IC |
| ADSP-1008AJD | Multiplier/Accumulator |
| ADSP-1008AJN | Multiplier/Accumulator |
| ADSP-1008AKD | Multiplier/Accumulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8506IDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8506IDWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8506IDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8507 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE |
| ADS8507I | 制造商:BB 制造商全稱:BB 功能描述:16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。