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參數(shù)資料
| 型號(hào)： | ADS8413IRGZTG4 |
| 英文描述： | 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，2 MSPS的LVDS串行接口，SAR類比數(shù)位轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/38頁 |
| 文件大小： | 1197K |
| 代理商： | ADS8413IRGZTG4 |
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ADS8413
SLAS490–OCTOBER 2005
TIMING REQUIREMENTS (continued)
T
A
= –40
°
C to 85
°
C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
REF
Figure 7
,
Figure 8
,
Figure 12
,
Figure 15
t
d16
Delay time, CLK_O to SDO and SYNC_O 3-state
4
ns
t
pd1
t
d17
Propagation delay time, SYNC_I to SYNC_O in daisy chain mode
11 + 0.5*t
CLK
ns
Figure 12
Delay time, SYNC_O and SDO 3-state to BUS_BUSY low in cascade mode.
0
2
ns
Figure 8
+VBD = 3.3 V
8
Delay time, RD rising edge to BUS_BUSY high for device with
LAT_Y/N = 1
Figure 11
,
Figure 14
t
d18
ns
+VBD = 5 V
7
+VBD = 3.3 V
40.5
Delay time, point A indicating clear for bus 3-state release to BUSY
falling edge
t
d19
ns
Figure 6
+VBD = 5 V
40
t
r
t
f
Rise time, differential LVDS output signal
950
ps
Figure 53
Fall time, differential LVDS output signal
950
ps
Figure 53
CLK frequency (serial data rate)
190
210
MHz
Figure 22
,
Figure 23
t
d20
Delay time, from PD falling edge to SDO 3-state
10
ns
Figure 22
,
Figure 23
t
d21
Delay time, from PD falling edge to device powerdown
10
μ
s
Figure 22
,
Figure 23
t
d22
Delay time, from PD rising edge to device powerup
25
ms
t
s1
t
d23
t
d24
Settling time, internal reference after first three conversions
4
ms
Figure 22
Delay time, CONVST falling edge to start of restricted zone for start of data read cycle
335
ns
Figure 9
Delay time, CONVST falling edge to end of restricted zone for start of data read cycle
406
ns
Figure 9
6
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