參數(shù)資料
型號(hào)： ADS8413IRGZTG4
英文描述： 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
中文描述： 16位，2 MSPS的LVDS串行接口，SAR類比數(shù)位轉(zhuǎn)換器
文件頁(yè)數(shù)： 11/38頁(yè)
文件大?。?/td> 1197K
代理商： ADS8413IRGZTG4
www.ti.com
BUS BUSY
SYNC_O
CLK_O
RD
1F
1R
2R
18F
SDO
D15
D14
D0
See Figures 5 and 6
See Figures 7 and 8
18R
DATA READ IN BYTE MODE
BUS BUSY
SYNC_O
CLK_O
RD
1F
1R
2R
18F
SDO
D15
D14
D7
D0
18R
9R
9F
10R
D8
ADS8413
SLAS490–OCTOBER 2005
Figure 3. Data Read With CS Low and BYTE = 0
As shown in
Figure 3
, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is
in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets
BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to rising edge)
if BYTE i/p is held low and can be used to synchronize a data frame. The clock count begins with the first CLK_O
falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each
subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling
edges of the clock. The next rising edge of SYNC_O coincides with the 16th rising edge of the clock. D0 is
latched out on the 17th rising edge of the clock. The receiver can latch the de-serialized 16-bit word on the 18th
rising edge (18R, or the second rising edge after a SYNC_O rising edge).
CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the
next data read cycle.
Byte mode is selected by setting BYTE = 1, this mode is allowed for any condition listed in
Table 1
.
Figure 4
shows a data read operation in byte mode.
Figure 4. Data Read Timing Diagram with CS Low and BYTE = 1
Similar to
Figure 3
, a new data read cycle is initiated with the falling edge of RD, if CS is low and device is in a
wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY
high at the start of the read cycle. The SYNC_O cycle is 8 clocks wide (rising edge to rising edge) if BYTE i/p is
held high and can be used to synchronize a data frame. The clock count begins with the first CLK_O falling edge
after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each subsequent data
bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling edges of clock. The
next rising edge of SYNC_O coincides with the 8th rising edge of the clock. D8 is latched out on the 9th rising
edge of the clock. The receiver can latch the de-serialized higher byte on the 10th rising edge (10R, or second
rising edge after a SYNC_O rising edge). The de-serialized lower byte can be latched on the 18th rising edge
(18R).
11
相關(guān)PDF資料
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