參數(shù)資料
型號(hào)： ADS8413IRGZRG4
英文描述： 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
中文描述： 16位，2 MSPS的LVDS串行接口，SAR類比數(shù)位轉(zhuǎn)換器
文件頁(yè)數(shù)： 27/38頁(yè)
文件大小： 1197K
代理商： ADS8413IRGZRG4
www.ti.com
LAYOUT
TYPICAL CHARACTERISTICS
8
11013
121865
30724
230
0
20000
40000
60000
80000
100000
120000
140000
65504
65505
65506
Code
65507
65508
N
+VA = 5 V,
T
A
= 25
C,
f
s
= = 4.096 V
V
ref
8
8436
108126
20721
7
0
20000
40000
60000
80000
100000
120000
32763
32764
32765
32766
32767
Code
N
+VA = 5 V,
T
A
= 25
C,
f
s
= = 4.096 V
V
ref
14.75
14.8
14.85
14.9
14.95
15
15.05
15.1
15.15
15.2
15.25
40
20
0
20
40
60
80
E
T
A
Free-Air Temperature
°
C
+VA = 5 V,
f
i
= 1 kHz,
f
s
= 2 MSPS,
V
ref
= 4.096 V
ADS8413
SLAS490–OCTOBER 2005
For optimum performance, care should be taken with the physical layout of the ADS8413 circuitry. The device
offers single-supply operation, and it is often used in close proximity with digital logic, FPGA, microcontrollers,
microprocessors, and digital signal processors. The more digital logic present in the design and the higher the
switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to the end of sampling and just prior to latching the output of
the analog comparator during the conversion phase. Such glitches might originate from switching power supplies,
nearby digital logic, or high power devices. Noise during the end of sampling and the later half of a conversion
must be kept to a minimum (the former half of a conversion is not very sensitive since the device uses a
proprietary error correction algorithm to correct for transient errors during this period).
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event. On average, the device draws very little current from an external reference as the reference
voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it
can drive the bypass capacitor or capacitors without oscillation. A 0.1-
μ
F bypass capacitor and 1-
μ
F storage
capacitor are recommended from REFIN directly to REFM.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a +5-V power supply plane that is separate from the
connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to
the ADC should be clean and well bypassed. A 0.1-
μ
F ceramic bypass capacitor should be placed as close to
the device as possible. See
Table 5
for the placement of the capacitor. In addition to the 0.1-
μ
F capacitor, a 1-
μ
F
capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-
μ
F
electrolytic capacitor or even a Pi filter made up of inductors and capacitors; all designed to essentially low-pass
filter the +5-V supply, thus removing the high frequency noise.
Table 5. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
SUPPLY PINS
Pair of pins require a shortest path to decoupling
capacitors
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
(9,10) (16,17) (20,21) (22,23) (26,27 or 25,26)
(36,37)
(44,45)
HISTOGRAM (DC CODE SPREAD
AT THE CENTER OF CODE)
HISTOGRAM (DC CODE SPREAD
WITH I/P CLOSE TO FS)
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
Figure 24.
Figure 25.
Figure 26.
27
相關(guān)PDF資料
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ADS8506 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
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