參數(shù)資料
型號(hào): ADS8413IRGZRG4
英文描述: 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
中文描述: 16位,2 MSPS的LVDS串行接口,SAR類(lèi)比數(shù)位轉(zhuǎn)換器
文件頁(yè)數(shù): 20/38頁(yè)
文件大?。?/td> 1197K
代理商: ADS8413IRGZRG4
www.ti.com
BUS_BUSY #1
RD #2
SYNC_O #1
CLK_O #1
t
d16
LSB #1
LSB 1
#1
SDO #1
CS = 0
15R
16R
17R
18R
BUSY_BUS #2 = 1
SYNC_O #2
MSB
MSB 1
t
d17
t
d13
SDO #2
1F #2
2R #2
THEORY OF OPERATION
ANALOG INPUT
ADS8413
SLAS490–OCTOBER 2005
Figure 15. Device
n
Read Cycle End and Device
n+1
Read Cycle Start
Unlike daisy chain, the data frames of all the devices in cascade are not seamless and there is a loss of time
between one device 3-state to other device data valid due to wakeup time from 3-state and a two clock phase
shift between SYNC and data (see
Figure 15
for details). As a result, the number of data frames per second in
this mode is less than in daisy chain mode. Also, a maximum of 4 devices can be cascaded on the same bus.
But, I/O power per device is considerably lower in cascade as compared to daisy chain as each device LVDS o/p
goes to 3-state after its data transfer. The deserializer at the output of the last device can shift the data on every
clock falling edge, and it can latch the parallel 16-bit word on the second CLK_O rising edge (shown as 18R)
after every SYNC_O rising edge.
The ADS8413 is a member of the high-speed successive approximation register (SAR) analog-to-digital
converters family. The architecture is based on charge redistribution, which inherently includes a sample/hold
function. The device includes a built-in conversion clock, internal reference, and 200-MHz LVDS serial interface.
The device can be operated at maximum throughput of 2 MSPS.
An analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the voltage difference
between these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
20
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ADS8506 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
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